CN100370601C - 一种形成集成半导体结构的方法 - Google Patents

一种形成集成半导体结构的方法 Download PDF

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Publication number
CN100370601C
CN100370601C CNB2005100773265A CN200510077326A CN100370601C CN 100370601 C CN100370601 C CN 100370601C CN B2005100773265 A CNB2005100773265 A CN B2005100773265A CN 200510077326 A CN200510077326 A CN 200510077326A CN 100370601 C CN100370601 C CN 100370601C
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China
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semiconductor
layer
base
orientation
annealing
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Expired - Fee Related
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CNB2005100773265A
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Chinese (zh)
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CN1728362A (zh
Inventor
凯文·K·陈
乔尔·P·德索扎
亚历山大·雷兹奈斯克
德维德拉·K·萨达纳
凯瑟琳·L·塞格尔
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D87/00—Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1908—Preparing SOI wafers using silicon implanted buried insulating layers, e.g. oxide layers [SIMOX]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/061—Manufacture or treatment using SOI processes together with lateral isolation, e.g. combinations of SOI and shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
CNB2005100773265A 2004-07-29 2005-06-20 一种形成集成半导体结构的方法 Expired - Fee Related CN100370601C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/902,557 US7253034B2 (en) 2004-07-29 2004-07-29 Dual SIMOX hybrid orientation technology (HOT) substrates
US10/902,557 2004-07-29

Publications (2)

Publication Number Publication Date
CN1728362A CN1728362A (zh) 2006-02-01
CN100370601C true CN100370601C (zh) 2008-02-20

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CNB2005100773265A Expired - Fee Related CN100370601C (zh) 2004-07-29 2005-06-20 一种形成集成半导体结构的方法

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US (1) US7253034B2 (enExample)
JP (1) JP5044808B2 (enExample)
CN (1) CN100370601C (enExample)
TW (1) TWI349972B (enExample)

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US7253034B2 (en) * 2004-07-29 2007-08-07 International Business Machines Corporation Dual SIMOX hybrid orientation technology (HOT) substrates
JP2006210432A (ja) * 2005-01-25 2006-08-10 Nec Electronics Corp 基板の製造方法
US7358164B2 (en) * 2005-06-16 2008-04-15 International Business Machines Corporation Crystal imprinting methods for fabricating substrates with thin active silicon layers
US7473985B2 (en) * 2005-06-16 2009-01-06 International Business Machines Corporation Hybrid oriented substrates and crystal imprinting methods for forming such hybrid oriented substrates
US7439108B2 (en) * 2005-06-16 2008-10-21 International Business Machines Corporation Coplanar silicon-on-insulator (SOI) regions of different crystal orientations and methods of making the same
US7344962B2 (en) * 2005-06-21 2008-03-18 International Business Machines Corporation Method of manufacturing dual orientation wafers
JP4566141B2 (ja) 2005-07-06 2010-10-20 株式会社リコー 設置角度調整装置及び設置角度調整方法
KR100655437B1 (ko) * 2005-08-09 2006-12-08 삼성전자주식회사 반도체 웨이퍼 및 그 제조방법
US20070040235A1 (en) 2005-08-19 2007-02-22 International Business Machines Corporation Dual trench isolation for CMOS with hybrid orientations
US7250656B2 (en) 2005-08-19 2007-07-31 International Business Machines Corporation Hybrid-orientation technology buried n-well design
US7352034B2 (en) * 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7396407B2 (en) * 2006-04-18 2008-07-08 International Business Machines Corporation Trench-edge-defect-free recrystallization by edge-angle-optimized solid phase epitaxy: method and applications to hybrid orientation substrates
US7452784B2 (en) * 2006-05-25 2008-11-18 International Business Machines Corporation Formation of improved SOI substrates using bulk semiconductor wafers
US7820501B2 (en) * 2006-10-11 2010-10-26 International Business Machines Corporation Decoder for a stationary switch machine
US20080169535A1 (en) * 2007-01-12 2008-07-17 International Business Machines Corporation Sub-lithographic faceting for mosfet performance enhancement
US7393738B1 (en) * 2007-01-16 2008-07-01 International Business Machines Corporation Subground rule STI fill for hot structure
US8016941B2 (en) * 2007-02-05 2011-09-13 Infineon Technologies Ag Method and apparatus for manufacturing a semiconductor
US7651902B2 (en) * 2007-04-20 2010-01-26 International Business Machines Corporation Hybrid substrates and methods for forming such hybrid substrates
US7750406B2 (en) * 2007-04-20 2010-07-06 International Business Machines Corporation Design structure incorporating a hybrid substrate
FR2915318B1 (fr) * 2007-04-20 2009-07-17 St Microelectronics Crolles 2 Procede de realisation d'un circuit electronique integre a deux portions de couches actives ayant des orientations cristallines differentes
FR2917235B1 (fr) 2007-06-06 2010-09-03 Soitec Silicon On Insulator Procede de realisation de composants hybrides.
US7989306B2 (en) * 2007-06-29 2011-08-02 International Business Machines Corporation Method of forming alternating regions of Si and SiGe or SiGeC on a buried oxide layer on a substrate
US8803195B2 (en) * 2007-08-02 2014-08-12 Wisconsin Alumni Research Foundation Nanomembrane structures having mixed crystalline orientations and compositions
US8039401B2 (en) * 2007-12-14 2011-10-18 Fairchild Semiconductor Corporation Structure and method for forming hybrid substrate
US8274115B2 (en) * 2008-03-19 2012-09-25 Globalfoundries Singapore Pte. Ltd. Hybrid orientation substrate with stress layer
US7528027B1 (en) 2008-03-25 2009-05-05 International Business Machines Corporation Structure and method for manufacturing device with ultra thin SOI at the tip of a V-shape channel
FR2942674B1 (fr) * 2009-02-27 2011-12-16 Commissariat Energie Atomique Procede d'elaboration d'un substrat hybride par recristallisation partielle d'une couche mixte
FR2954584B1 (fr) * 2009-12-22 2013-07-19 Commissariat Energie Atomique Substrat hybride a isolation amelioree et procede de realisation simplifie d'un substrat hybride
US9490161B2 (en) * 2014-04-29 2016-11-08 International Business Machines Corporation Channel SiGe devices with multiple threshold voltages on hybrid oriented substrates, and methods of manufacturing same
DE102019100312A1 (de) * 2019-01-08 2020-07-09 Parcan NanoTech Co. Ltd. Substrat für eine kontrollierte lonenimplantation und Verfahren zur Herstellung eines Substrats für eine kontrollierte lonenimplantation

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CN1467795A (zh) * 2002-06-07 2004-01-14 ������������ʽ���� 半导体衬底的制造方法和半导体器件的制造方法
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Also Published As

Publication number Publication date
TW200610063A (en) 2006-03-16
TWI349972B (en) 2011-10-01
JP2006041526A (ja) 2006-02-09
CN1728362A (zh) 2006-02-01
US20060024931A1 (en) 2006-02-02
US7253034B2 (en) 2007-08-07
JP5044808B2 (ja) 2012-10-10

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