JP2005537672A5 - - Google Patents

Download PDF

Info

Publication number
JP2005537672A5
JP2005537672A5 JP2004533596A JP2004533596A JP2005537672A5 JP 2005537672 A5 JP2005537672 A5 JP 2005537672A5 JP 2004533596 A JP2004533596 A JP 2004533596A JP 2004533596 A JP2004533596 A JP 2004533596A JP 2005537672 A5 JP2005537672 A5 JP 2005537672A5
Authority
JP
Japan
Prior art keywords
layer
insulating means
sige
sige layer
parallel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2004533596A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005537672A (ja
Filing date
Publication date
Priority claimed from GBGB0220438.6A external-priority patent/GB0220438D0/en
Application filed filed Critical
Publication of JP2005537672A publication Critical patent/JP2005537672A/ja
Publication of JP2005537672A5 publication Critical patent/JP2005537672A5/ja
Pending legal-status Critical Current

Links

JP2004533596A 2002-09-03 2003-08-12 格子調整半導体基板の形成 Pending JP2005537672A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GBGB0220438.6A GB0220438D0 (en) 2002-09-03 2002-09-03 Formation of lattice-turning semiconductor substrates
PCT/GB2003/003514 WO2004023536A1 (en) 2002-09-03 2003-08-12 Formation of lattice-tuning semiconductor substrates

Publications (2)

Publication Number Publication Date
JP2005537672A JP2005537672A (ja) 2005-12-08
JP2005537672A5 true JP2005537672A5 (cg-RX-API-DMAC10.html) 2008-12-18

Family

ID=9943412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004533596A Pending JP2005537672A (ja) 2002-09-03 2003-08-12 格子調整半導体基板の形成

Country Status (8)

Country Link
US (1) US7179727B2 (cg-RX-API-DMAC10.html)
EP (1) EP1540715A1 (cg-RX-API-DMAC10.html)
JP (1) JP2005537672A (cg-RX-API-DMAC10.html)
KR (1) KR20050038037A (cg-RX-API-DMAC10.html)
CN (1) CN100364052C (cg-RX-API-DMAC10.html)
AU (1) AU2003251376A1 (cg-RX-API-DMAC10.html)
GB (1) GB0220438D0 (cg-RX-API-DMAC10.html)
WO (1) WO2004023536A1 (cg-RX-API-DMAC10.html)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2006011107A1 (en) * 2004-07-22 2006-02-02 Koninklijke Philips Electronics N.V. Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
GB2418531A (en) * 2004-09-22 2006-03-29 Univ Warwick Formation of lattice-tuning semiconductor substrates
US9153645B2 (en) 2005-05-17 2015-10-06 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8324660B2 (en) 2005-05-17 2012-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
JP5481067B2 (ja) 2005-07-26 2014-04-23 台湾積體電路製造股▲ふん▼有限公司 代替活性エリア材料の集積回路への組み込みのための解決策
US7638842B2 (en) 2005-09-07 2009-12-29 Amberwave Systems Corporation Lattice-mismatched semiconductor structures on insulators
WO2007112066A2 (en) 2006-03-24 2007-10-04 Amberwave Systems Corporation Lattice-mismatched semiconductor structures and related methods for device fabrication
US7476606B2 (en) * 2006-03-28 2009-01-13 Northrop Grumman Corporation Eutectic bonding of ultrathin semiconductors
EP2062290B1 (en) 2006-09-07 2019-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Defect reduction using aspect ratio trapping
US7875958B2 (en) * 2006-09-27 2011-01-25 Taiwan Semiconductor Manufacturing Company, Ltd. Quantum tunneling devices and circuits with lattice-mismatched semiconductor structures
WO2008051503A2 (en) * 2006-10-19 2008-05-02 Amberwave Systems Corporation Light-emitter-based devices with lattice-mismatched semiconductor structures
US8237151B2 (en) 2009-01-09 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Diode-based devices and methods for making the same
US7825328B2 (en) 2007-04-09 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Nitride-based multi-junction solar cell modules and methods for making the same
WO2008124154A2 (en) 2007-04-09 2008-10-16 Amberwave Systems Corporation Photovoltaics on silicon
US8304805B2 (en) 2009-01-09 2012-11-06 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor diodes fabricated by aspect ratio trapping with coalesced films
US8329541B2 (en) 2007-06-15 2012-12-11 Taiwan Semiconductor Manufacturing Company, Ltd. InP-based transistor fabrication
JP2010538495A (ja) 2007-09-07 2010-12-09 アンバーウェーブ・システムズ・コーポレーション 多接合太陽電池
CN103367115A (zh) * 2007-12-28 2013-10-23 住友化学株式会社 半导体基板、半导体基板的制造方法及电子器件
US8183667B2 (en) 2008-06-03 2012-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Epitaxial growth of crystalline material
US8274097B2 (en) 2008-07-01 2012-09-25 Taiwan Semiconductor Manufacturing Company, Ltd. Reduction of edge effects from aspect ratio trapping
US8981427B2 (en) 2008-07-15 2015-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Polishing of small composite semiconductor materials
EP2335273A4 (en) 2008-09-19 2012-01-25 Taiwan Semiconductor Mfg FORMATION OF EQUIPMENT BY EXCESSIVE GROWTH OF THE EPITAXIAL LAYER
US20100072515A1 (en) * 2008-09-19 2010-03-25 Amberwave Systems Corporation Fabrication and structures of crystalline material
US8253211B2 (en) 2008-09-24 2012-08-28 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor sensor structures with reduced dislocation defect densities
WO2010038462A1 (ja) * 2008-10-02 2010-04-08 住友化学株式会社 半導体デバイス用基板、半導体デバイス装置、設計システム、製造方法、および設計方法
US8629446B2 (en) 2009-04-02 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Devices formed from a non-polar plane of a crystalline material and method of making the same
CN102439696A (zh) * 2009-05-22 2012-05-02 住友化学株式会社 半导体基板及其制造方法、电子器件及其制造方法
JP6706414B2 (ja) * 2015-11-27 2020-06-10 国立研究開発法人情報通信研究機構 Ｇｅ単結晶薄膜の製造方法及び光デバイス

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5272105A (en) * 1988-02-11 1993-12-21 Gte Laboratories Incorporated Method of manufacturing an heteroepitaxial semiconductor structure
GB2215514A (en) * 1988-03-04 1989-09-20 Plessey Co Plc Terminating dislocations in semiconductor epitaxial layers
US5238869A (en) 1988-07-25 1993-08-24 Texas Instruments Incorporated Method of forming an epitaxial layer on a heterointerface
EP0380815B1 (en) 1989-01-31 1994-05-25 Agfa-Gevaert N.V. Integration of GaAs on Si substrate
US5158907A (en) * 1990-08-02 1992-10-27 At&T Bell Laboratories Method for making semiconductor devices with low dislocation defects
JPH04315419A (ja) * 1991-04-12 1992-11-06 Nec Corp 元素半導体基板上の絶縁膜／化合物半導体積層構造
US5442205A (en) * 1991-04-24 1995-08-15 At&T Corp. Semiconductor heterostructure devices with strained semiconductor layers
JP3286920B2 (ja) 1992-07-10 2002-05-27 富士通株式会社 半導体装置の製造方法
JPH06260427A (ja) * 1993-03-05 1994-09-16 Nec Corp 半導体膜の選択成長方法
US6039803A (en) * 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
EP1036412A1 (en) 1997-09-16 2000-09-20 Massachusetts Institute Of Technology CO-PLANAR Si AND Ge COMPOSITE SUBSTRATE AND METHOD OF PRODUCING SAME
DE19802977A1 (de) 1998-01-27 1999-07-29 Forschungszentrum Juelich Gmbh Verfahren zur Herstellung einer einkristallinen Schicht auf einem nicht gitterangepaßten Substrat, sowie eine oder mehrere solcher Schichten enthaltendes Bauelement
JP3587081B2 (ja) 1999-05-10 2004-11-10 豊田合成株式会社 Ｉｉｉ族窒化物半導体の製造方法及びｉｉｉ族窒化物半導体発光素子
DE60045126D1 (de) * 1999-06-25 2010-12-02 Massachusetts Inst Technology Oxidation einer auf einer germaniumschicht aufgebrachten siliziumschicht
JP4406995B2 (ja) * 2000-03-27 2010-02-03 パナソニック株式会社 半導体基板および半導体基板の製造方法
JP4269541B2 (ja) * 2000-08-01 2009-05-27 株式会社Ｓｕｍｃｏ 半導体基板と電界効果型トランジスタ並びにＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
JP4345244B2 (ja) * 2001-05-31 2009-10-14 株式会社Ｓｕｍｃｏ ＳｉＧｅ層の形成方法及びこれを用いた歪みＳｉ層の形成方法と電界効果型トランジスタの製造方法
JP2004055943A (ja) * 2002-07-23 2004-02-19 Matsushita Electric Ind Co Ltd 半導体装置とその製造方法

Similar Documents

Publication Publication Date Title
US6982208B2 (en) Method for producing high throughput strained-Si channel MOSFETS
US9337026B2 (en) Graphene growth on a carbon-containing semiconductor layer
KR101548013B1 (ko) 채널의 변형을 조절하기 위한 응력 부재
JP4686480B2 (ja) 高度な緩和及び低い積層欠陥密度を有する薄いＳｉＧｅオン・インシュレータ（ＳＧＯＩ）ウェハを形成する方法。
US20150206743A1 (en) Silicon carbide epitaxy
CN101140864B (zh) 半导体异质结构和形成半导体异质结构的方法
JP5230116B2 (ja) 高配向性シリコン薄膜の形成方法、３次元半導体素子の製造方法及び３次元半導体素子
WO2003063229A1 (en) METHOD OF CREATING HIGH-QUALITY RELAXED SiGe-ON-INSULATOR FOR STRAINED Si CMOS APPLICATIONS
JP2017119624A (ja) 半導体デバイス用基板
JP2008516449A (ja) シリコンゲルマニウム層の低温選択エピタキシャル成長
TW200834667A (en) Formation of epitaxial layers containing silicon
WO2003103031A3 (en) Formation of lattice-tuning semiconductor substrates
JP2005537672A (ja) 格子調整半導体基板の形成
JPH11162850A (ja) 炭化珪素基板およびその製造方法、並びに炭化珪素基板を用いた半導体素子
WO2004049411A1 (ja) 半導体基板の製造方法及び電界効果型タランジスタの製造方法並びに半導体基板及び電界効果型トランジスタ
JP2006080278A (ja) 歪みシリコンウエハおよびその製造方法
KR100679737B1 (ko) 왜곡층을 가지는 실리콘기판의 제조방법
JP4213896B2 (ja) 半導体基板の製造方法
US20050170577A1 (en) Strained silicon layer fabrication with reduced dislocation defect density
JP2004521489A5 (cg-RX-API-DMAC10.html)
EP3844819B1 (en) Method for making superlattice structures with reduced defect densities
US7202142B2 (en) Method for producing low defect density strained -Si channel MOSFETS
Konno et al. Low-temperature heteroepitaxial growth of 3C-SiC (111) on Si (110) substrate using monomethylsilane
JP2000269476A5 (cg-RX-API-DMAC10.html)
US20070212879A1 (en) Formation of lattice-tuning semiconductor substrates