JP2005531934A - 複数のゲートレイヤを用いて論理要素を製造する技術 - Google Patents

複数のゲートレイヤを用いて論理要素を製造する技術 Download PDF

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Publication number
JP2005531934A
JP2005531934A JP2004519678A JP2004519678A JP2005531934A JP 2005531934 A JP2005531934 A JP 2005531934A JP 2004519678 A JP2004519678 A JP 2004519678A JP 2004519678 A JP2004519678 A JP 2004519678A JP 2005531934 A JP2005531934 A JP 2005531934A
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Japan
Prior art keywords
gate
region
gate structure
substrate
logic element
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Pending
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JP2004519678A
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English (en)
Japanese (ja)
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JP2005531934A5 (https=
Inventor
モクレージ、ニーマ
ルッツェ、ジェフリー
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SanDisk Corp
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SanDisk Corp
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Publication date
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of JP2005531934A publication Critical patent/JP2005531934A/ja
Publication of JP2005531934A5 publication Critical patent/JP2005531934A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
JP2004519678A 2002-07-02 2003-06-25 複数のゲートレイヤを用いて論理要素を製造する技術 Pending JP2005531934A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US42111502P 2002-07-02 2002-07-02
US10/211,433 US7064034B2 (en) 2002-07-02 2002-08-02 Technique for fabricating logic elements using multiple gate layers
PCT/US2003/020453 WO2004006338A1 (en) 2002-07-02 2003-06-25 Technique for fabricating logic elements using multiple gate layers

Publications (2)

Publication Number Publication Date
JP2005531934A true JP2005531934A (ja) 2005-10-20
JP2005531934A5 JP2005531934A5 (https=) 2007-01-11

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ID=30117870

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004519678A Pending JP2005531934A (ja) 2002-07-02 2003-06-25 複数のゲートレイヤを用いて論理要素を製造する技術

Country Status (5)

Country Link
US (3) US7064034B2 (https=)
EP (1) EP1520302A1 (https=)
JP (1) JP2005531934A (https=)
AU (1) AU2003281425A1 (https=)
WO (1) WO2004006338A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012222273A (ja) * 2011-04-13 2012-11-12 Lapis Semiconductor Co Ltd 半導体集積回路、半導体集積回路の製造方法及び信号処理装置
JP2015056472A (ja) * 2013-09-11 2015-03-23 株式会社東芝 半導体装置

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101025846B1 (ko) * 2004-09-13 2011-03-30 삼성전자주식회사 탄소나노튜브 채널을 포함하는 반도체 장치의 트랜지스터
WO2007017700A1 (en) 2005-08-09 2007-02-15 University Of Sunderland Hydrophobic silica particles and methods of making same
US7968932B2 (en) * 2005-12-26 2011-06-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7738282B2 (en) * 2007-02-15 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure of dual port SRAM
CN102024821B (zh) * 2009-09-18 2012-08-22 中芯国际集成电路制造(上海)有限公司 非易失性存储装置、非易失性存储器件及其制造方法
JP5531848B2 (ja) * 2010-08-06 2014-06-25 富士通セミコンダクター株式会社 半導体装置、半導体集積回路装置、ＳＲＡＭ、Ｄｔ−ＭＯＳトランジスタの製造方法
CN102569386B (zh) * 2010-12-17 2015-02-04 上海华虹宏力半导体制造有限公司 具有屏蔽栅的vdmos器件及其制备方法
CN102569385B (zh) * 2010-12-17 2015-04-08 上海华虹宏力半导体制造有限公司 具有屏蔽栅的vdmos结构及其制备方法
US9735382B2 (en) * 2012-11-08 2017-08-15 Palo Alto Research Center Incorporated Circuit layout for thin film transistors in series or parallel
US8778742B1 (en) * 2013-04-26 2014-07-15 Freescale Semiconductor, Inc. Methods and systems for gate dimension control in multi-gate structures for semiconductor devices
KR102374052B1 (ko) 2016-02-26 2022-03-14 삼성전자주식회사 반도체 소자 및 그 제조 방법

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4931592B1 (https=) * 1965-12-22 1974-08-22
JPS6340361A (ja) * 1986-08-05 1988-02-20 Oki Electric Ind Co Ltd 相補型半導体装置
JPS6340360A (ja) * 1986-08-05 1988-02-20 Oki Electric Ind Co Ltd 半導体装置
JPS6355975A (ja) * 1986-08-27 1988-03-10 Hitachi Ltd 半導体装置
JPH03247117A (ja) * 1990-02-26 1991-11-05 Nec Corp Ｃｍｏｓ論理回路
JPH03283566A (ja) * 1990-03-30 1991-12-13 Nec Corp 半導体装置
JPH0433374A (ja) * 1990-05-30 1992-02-04 Fujitsu Ltd 電界効果半導体装置
JPH09186332A (ja) * 1995-12-28 1997-07-15 Furontetsuku:Kk 電界効果トランジスタおよびその駆動方法
JPH09260660A (ja) * 1996-03-26 1997-10-03 Sharp Corp トランジスタ
JP2000058849A (ja) * 1998-08-17 2000-02-25 Nec Corp 薄膜半導体装置
JP2000077627A (ja) * 1998-06-17 2000-03-14 Mitsubishi Electric Corp 半導体素子
JP2001326289A (ja) * 2000-03-08 2001-11-22 Semiconductor Energy Lab Co Ltd 不揮発性メモリおよび半導体装置
JP2001358335A (ja) * 2000-05-01 2001-12-26 Hynix Semiconductor Inc 半導体装置

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DE2734354A1 (de) * 1977-07-29 1979-02-08 Siemens Ag Speicherelement
DE2935254A1 (de) * 1979-08-31 1981-04-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung einer monolithischen statischen speicherzelle
US4380863A (en) * 1979-12-10 1983-04-26 Texas Instruments Incorporated Method of making double level polysilicon series transistor devices
US4409723A (en) * 1980-04-07 1983-10-18 Eliyahou Harari Method of forming non-volatile EPROM and EEPROM with increased efficiency
US4749443A (en) * 1986-12-04 1988-06-07 Texas Instruments Incorporated Sidewall oxide to reduce filaments
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US5296393A (en) 1990-11-23 1994-03-22 Texas Instruments Incorporated Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods
US5204541A (en) 1991-06-28 1993-04-20 Texas Instruments Incorporated Gated thyristor and process for its simultaneous fabrication with high- and low-voltage semiconductor devices
US5210047A (en) * 1991-12-12 1993-05-11 Woo Been Jon K Process for fabricating a flash EPROM having reduced cell size
US5366918A (en) 1994-02-07 1994-11-22 United Microelectronics Corporation Method for fabricating a split polysilicon SRAM cell
JP3396286B2 (ja) 1994-02-28 2003-04-14 三菱電機株式会社 半導体集積回路装置およびその製造方法
US6031981A (en) 1996-12-19 2000-02-29 Cirrus Logic, Inc. Reconfigurable gate array cells for automatic engineering change order
US5953599A (en) 1997-06-12 1999-09-14 National Semiconductor Corporation Method for forming low-voltage CMOS transistors with a thin layer of gate oxide and high-voltage CMOS transistors with a thick layer of gate oxide
US5851881A (en) 1997-10-06 1998-12-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making monos flash memory for multi-level logic
US6133102A (en) 1998-06-19 2000-10-17 Wu; Shye-Lin Method of fabricating double poly-gate high density multi-state flat mask ROM cells
US6323103B1 (en) 1998-10-20 2001-11-27 Siemens Aktiengesellschaft Method for fabricating transistors
US6313500B1 (en) 1999-01-12 2001-11-06 Agere Systems Guardian Corp. Split gate memory cell

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Publication number Priority date Publication date Assignee Title
JPS4931592B1 (https=) * 1965-12-22 1974-08-22
JPS6340361A (ja) * 1986-08-05 1988-02-20 Oki Electric Ind Co Ltd 相補型半導体装置
JPS6340360A (ja) * 1986-08-05 1988-02-20 Oki Electric Ind Co Ltd 半導体装置
JPS6355975A (ja) * 1986-08-27 1988-03-10 Hitachi Ltd 半導体装置
JPH03247117A (ja) * 1990-02-26 1991-11-05 Nec Corp Ｃｍｏｓ論理回路
JPH03283566A (ja) * 1990-03-30 1991-12-13 Nec Corp 半導体装置
JPH0433374A (ja) * 1990-05-30 1992-02-04 Fujitsu Ltd 電界効果半導体装置
JPH09186332A (ja) * 1995-12-28 1997-07-15 Furontetsuku:Kk 電界効果トランジスタおよびその駆動方法
JPH09260660A (ja) * 1996-03-26 1997-10-03 Sharp Corp トランジスタ
JP2000077627A (ja) * 1998-06-17 2000-03-14 Mitsubishi Electric Corp 半導体素子
JP2000058849A (ja) * 1998-08-17 2000-02-25 Nec Corp 薄膜半導体装置
JP2001326289A (ja) * 2000-03-08 2001-11-22 Semiconductor Energy Lab Co Ltd 不揮発性メモリおよび半導体装置
JP2001358335A (ja) * 2000-05-01 2001-12-26 Hynix Semiconductor Inc 半導体装置

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012222273A (ja) * 2011-04-13 2012-11-12 Lapis Semiconductor Co Ltd 半導体集積回路、半導体集積回路の製造方法及び信号処理装置
JP2015056472A (ja) * 2013-09-11 2015-03-23 株式会社東芝 半導体装置

Also Published As

Publication number Publication date
AU2003281425A1 (en) 2004-01-23
US7265423B2 (en) 2007-09-04
US20060202258A1 (en) 2006-09-14
US20070023838A1 (en) 2007-02-01
US7064034B2 (en) 2006-06-20
EP1520302A1 (en) 2005-04-06
US7425744B2 (en) 2008-09-16
US20040038482A1 (en) 2004-02-26
WO2004006338A1 (en) 2004-01-15

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