AU2003281425A1 - Technique for fabricating logic elements using multiple gate layers - Google Patents

Technique for fabricating logic elements using multiple gate layers

Info

Publication number
AU2003281425A1
AU2003281425A1 AU2003281425A AU2003281425A AU2003281425A1 AU 2003281425 A1 AU2003281425 A1 AU 2003281425A1 AU 2003281425 A AU2003281425 A AU 2003281425A AU 2003281425 A AU2003281425 A AU 2003281425A AU 2003281425 A1 AU2003281425 A1 AU 2003281425A1
Authority
AU
Australia
Prior art keywords
technique
logic elements
gate layers
multiple gate
fabricating logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003281425A
Other languages
English (en)
Inventor
Jeffrey Lutze
Nima Mokhlesi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SanDisk Corp
Original Assignee
SanDisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SanDisk Corp filed Critical SanDisk Corp
Publication of AU2003281425A1 publication Critical patent/AU2003281425A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/031—Manufacture or treatment of data-storage electrodes
    • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0135—Manufacturing their gate conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B10/00—Static random access memory [SRAM] devices
    • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/903—FET configuration adapted for use as static memory cell
AU2003281425A 2002-07-02 2003-06-25 Technique for fabricating logic elements using multiple gate layers Abandoned AU2003281425A1 (en)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US42111502P 2002-07-02 2002-07-02
US60/421,115 2002-07-02
US10/211,433 US7064034B2 (en) 2002-07-02 2002-08-02 Technique for fabricating logic elements using multiple gate layers
US10/211,433 2002-08-02
PCT/US2003/020453 WO2004006338A1 (en) 2002-07-02 2003-06-25 Technique for fabricating logic elements using multiple gate layers

Publications (1)

Publication Number Publication Date
AU2003281425A1 true AU2003281425A1 (en) 2004-01-23

Family

ID=30117870

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003281425A Abandoned AU2003281425A1 (en) 2002-07-02 2003-06-25 Technique for fabricating logic elements using multiple gate layers

Country Status (5)

Country Link
US (3) US7064034B2 (https=)
EP (1) EP1520302A1 (https=)
JP (1) JP2005531934A (https=)
AU (1) AU2003281425A1 (https=)
WO (1) WO2004006338A1 (https=)

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WO2007017700A1 (en) 2005-08-09 2007-02-15 University Of Sunderland Hydrophobic silica particles and methods of making same
US7968932B2 (en) * 2005-12-26 2011-06-28 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US7738282B2 (en) * 2007-02-15 2010-06-15 Taiwan Semiconductor Manufacturing Company, Ltd. Cell structure of dual port SRAM
CN102024821B (zh) * 2009-09-18 2012-08-22 中芯国际集成电路制造(上海)有限公司 非易失性存储装置、非易失性存储器件及其制造方法
JP5531848B2 (ja) * 2010-08-06 2014-06-25 富士通セミコンダクター株式会社 半導体装置、半導体集積回路装置、ＳＲＡＭ、Ｄｔ−ＭＯＳトランジスタの製造方法
CN102569386B (zh) * 2010-12-17 2015-02-04 上海华虹宏力半导体制造有限公司 具有屏蔽栅的vdmos器件及其制备方法
CN102569385B (zh) * 2010-12-17 2015-04-08 上海华虹宏力半导体制造有限公司 具有屏蔽栅的vdmos结构及其制备方法
JP5715872B2 (ja) * 2011-04-13 2015-05-13 ラピスセミコンダクタ株式会社 半導体集積回路、半導体集積回路の製造方法及び信号処理装置
US9735382B2 (en) * 2012-11-08 2017-08-15 Palo Alto Research Center Incorporated Circuit layout for thin film transistors in series or parallel
US8778742B1 (en) * 2013-04-26 2014-07-15 Freescale Semiconductor, Inc. Methods and systems for gate dimension control in multi-gate structures for semiconductor devices
JP2015056472A (ja) * 2013-09-11 2015-03-23 株式会社東芝 半導体装置
KR102374052B1 (ko) 2016-02-26 2022-03-14 삼성전자주식회사 반도체 소자 및 그 제조 방법

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DE2734354A1 (de) * 1977-07-29 1979-02-08 Siemens Ag Speicherelement
DE2935254A1 (de) * 1979-08-31 1981-04-02 Siemens AG, 1000 Berlin und 8000 München Verfahren zur herstellung einer monolithischen statischen speicherzelle
US4380863A (en) * 1979-12-10 1983-04-26 Texas Instruments Incorporated Method of making double level polysilicon series transistor devices
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US5296393A (en) 1990-11-23 1994-03-22 Texas Instruments Incorporated Process for the simultaneous fabrication of high-and-low-voltage semiconductor devices, integrated circuit containing the same, systems and methods
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JP3396286B2 (ja) 1994-02-28 2003-04-14 三菱電機株式会社 半導体集積回路装置およびその製造方法
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Also Published As

Publication number Publication date
US7265423B2 (en) 2007-09-04
JP2005531934A (ja) 2005-10-20
US20060202258A1 (en) 2006-09-14
US20070023838A1 (en) 2007-02-01
US7064034B2 (en) 2006-06-20
EP1520302A1 (en) 2005-04-06
US7425744B2 (en) 2008-09-16
US20040038482A1 (en) 2004-02-26
WO2004006338A1 (en) 2004-01-15

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase