JP2005522033A5 - - Google Patents

Download PDF

Info

Publication number
JP2005522033A5
JP2005522033A5 JP2003581249A JP2003581249A JP2005522033A5 JP 2005522033 A5 JP2005522033 A5 JP 2005522033A5 JP 2003581249 A JP2003581249 A JP 2003581249A JP 2003581249 A JP2003581249 A JP 2003581249A JP 2005522033 A5 JP2005522033 A5 JP 2005522033A5
Authority
JP
Japan
Prior art keywords
dopant
ion
oxide
steps
liners
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2003581249A
Other languages
English (en)
Japanese (ja)
Other versions
JP2005522033A (ja
JP4514023B2 (ja
Filing date
Publication date
Priority claimed from US10/105,522 external-priority patent/US6583016B1/en
Application filed filed Critical
Publication of JP2005522033A publication Critical patent/JP2005522033A/ja
Publication of JP2005522033A5 publication Critical patent/JP2005522033A5/ja
Application granted granted Critical
Publication of JP4514023B2 publication Critical patent/JP4514023B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

JP2003581249A 2002-03-26 2003-03-13 ソース/ドレイン拡張部からドーパントが外方拡散しないようにするための、シリコン酸化物ライナーのイオン注入 Expired - Fee Related JP4514023B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/105,522 US6583016B1 (en) 2002-03-26 2002-03-26 Doped spacer liner for improved transistor performance
PCT/US2003/007559 WO2003083929A1 (en) 2002-03-26 2003-03-13 Ion implantation of silicon oxid liner to prevent dopant out-diffusion from so urce/drain extensions

Publications (3)

Publication Number Publication Date
JP2005522033A JP2005522033A (ja) 2005-07-21
JP2005522033A5 true JP2005522033A5 (enExample) 2006-04-27
JP4514023B2 JP4514023B2 (ja) 2010-07-28

Family

ID=22306307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003581249A Expired - Fee Related JP4514023B2 (ja) 2002-03-26 2003-03-13 ソース/ドレイン拡張部からドーパントが外方拡散しないようにするための、シリコン酸化物ライナーのイオン注入

Country Status (8)

Country Link
US (1) US6583016B1 (enExample)
EP (1) EP1488453A1 (enExample)
JP (1) JP4514023B2 (enExample)
KR (1) KR100948939B1 (enExample)
CN (1) CN100355046C (enExample)
AU (1) AU2003220198A1 (enExample)
TW (1) TWI270933B (enExample)
WO (1) WO2003083929A1 (enExample)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777298B2 (en) * 2002-06-14 2004-08-17 International Business Machines Corporation Elevated source drain disposable spacer CMOS
JP4112330B2 (ja) * 2002-10-02 2008-07-02 富士通株式会社 半導体装置の製造方法
JP2004363443A (ja) * 2003-06-06 2004-12-24 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US6812105B1 (en) * 2003-07-16 2004-11-02 International Business Machines Corporation Ultra-thin channel device with raised source and drain and solid source extension doping
CN1296987C (zh) * 2003-09-23 2007-01-24 茂德科技股份有限公司 接触孔的制造方法以及半导体元件的制造方法
CN100405581C (zh) * 2003-12-04 2008-07-23 国际商业机器公司 用于使用牺牲的注入层形成非无定形超薄半导体器件的方法
US20070029608A1 (en) * 2005-08-08 2007-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Offset spacers for CMOS transistors
KR100649311B1 (ko) * 2005-12-15 2006-11-24 동부일렉트로닉스 주식회사 게이트 스페이서를 이용한 피모스 소자의 변형된 채널층형성 방법 및 이 방법에 의해 형성된 피모스 소자
JP6087672B2 (ja) * 2012-03-16 2017-03-01 株式会社半導体エネルギー研究所 半導体装置
US9093554B2 (en) * 2012-05-14 2015-07-28 Globalfoundries Inc. Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers
US10141417B2 (en) 2015-10-20 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure, semiconductor device and the method of forming semiconductor device
US10770354B2 (en) 2017-11-15 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming integrated circuit with low-k sidewall spacers for gate stacks
CN110265481B (zh) * 2018-08-10 2023-01-17 友达光电股份有限公司 晶体管装置

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US165659A (en) * 1875-07-20 Improvement in registering board-rules
US619098A (en) * 1899-02-07 Steam-boiler
JPH0834313B2 (ja) * 1989-10-09 1996-03-29 株式会社東芝 半導体装置及びその製造方法
KR950000141B1 (ko) * 1990-04-03 1995-01-10 미쓰비시 뎅끼 가부시끼가이샤 반도체 장치 및 그 제조방법
JPH05267327A (ja) * 1992-03-18 1993-10-15 Fujitsu Ltd Misfet及びその製造方法
JPH0823031A (ja) * 1994-07-05 1996-01-23 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JPH0897173A (ja) * 1994-09-22 1996-04-12 Sony Corp 半導体装置の製造方法
JPH08288504A (ja) * 1995-04-14 1996-11-01 Sony Corp 半導体装置の製造方法
CN1057867C (zh) * 1995-12-20 2000-10-25 台湾茂矽电子股份有限公司 注入磷形成补偿的器件沟道区的半导体器件的制造方法
US5756383A (en) * 1996-12-23 1998-05-26 Advanced Micro Devices Method of manufacturing an active region of a semiconductor by diffusing a counterdopant out of a sidewall spacer
US6117719A (en) * 1997-12-18 2000-09-12 Advanced Micro Devices, Inc. Oxide spacers as solid sources for gallium dopant introduction
JPH11238882A (ja) * 1998-02-23 1999-08-31 Sony Corp 半導体装置の製造方法
JP3425079B2 (ja) * 1998-04-24 2003-07-07 三菱電機株式会社 半導体装置の製造方法
US6162692A (en) * 1998-06-26 2000-12-19 Advanced Micro Devices, Inc. Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6190982B1 (en) * 2000-01-28 2001-02-20 United Microelectronics Corp. Method of fabricating a MOS transistor on a semiconductor wafer
US6346468B1 (en) * 2000-02-11 2002-02-12 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer using a disposable polysilicon spacer
US6235600B1 (en) * 2000-03-20 2001-05-22 Taiwan Semiconductor Manufacturing Company Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition
JP2001291861A (ja) * 2000-04-05 2001-10-19 Nec Corp Mosトランジスタ、トランジスタ製造方法
JP2002076336A (ja) * 2000-09-01 2002-03-15 Mitsubishi Electric Corp 半導体装置およびsoi基板
WO2003054951A1 (en) * 2001-12-19 2003-07-03 Advanced Micro Devices, Inc. Semiconductor device comprising a thin oxide liner and method of manufacturing the same
JP3966243B2 (ja) * 2003-07-09 2007-08-29 トヨタ自動車株式会社 内燃機関

Similar Documents

Publication Publication Date Title
US7535067B2 (en) Transistor in semiconductor devices and method of fabricating the same
US6124177A (en) Method for making deep sub-micron mosfet structures having improved electrical characteristics
CN101635312B (zh) 具有自对准损伤层的器件结构以及该器件结构的形成方法
US6660657B1 (en) Methods of incorporating nitrogen into silicon-oxide-containing layers
JP4633310B2 (ja) Mosトランジスタのゲルマニウムがドーピングされたポリシリコンゲートの形成方法及びこれを利用したcmosトランジスタの形成方法
JP2010161397A5 (enExample)
US8975708B2 (en) Semiconductor device with reduced contact resistance and method of manufacturing thereof
US8318571B2 (en) Method for forming P-type lightly doped drain region using germanium pre-amorphous treatment
JP2005522033A5 (enExample)
TW449836B (en) Manufacturing method and device for forming anti-punch-through region by large-angle-tilt implantation
CN100547793C (zh) 双栅cmos半导体器件及其制造方法
US5972761A (en) Method of making MOS transistors with a gate-side air-gap structure and an extension ultra-shallow S/D junction
US20050059260A1 (en) CMOS transistors and methods of forming same
US20080122017A1 (en) Semiconductor device and fabricating method thereof
JP4514023B2 (ja) ソース/ドレイン拡張部からドーパントが外方拡散しないようにするための、シリコン酸化物ライナーのイオン注入
JP2004508717A5 (enExample)
US6642134B2 (en) Semiconductor processing employing a semiconductor spacer
US20060001105A1 (en) Semiconductor device having optimized shallow junction geometries and method for fabrication thereof
US20060105518A1 (en) Ultra-shallow arsenic junction formation in silicon germanium
CN1848390A (zh) 降低多晶耗尽效应的制作多晶硅栅极晶体管的方法
JPH04343437A (ja) 半導体装置の製造方法
TW200537649A (en) A semiconductor device
KR101079873B1 (ko) 반도체 소자의 형성 방법
KR101150462B1 (ko) 반도체 소자의 제조 방법
JP2005517285A5 (enExample)