CN100355046C - 防止掺杂剂自源极/漏极延伸部向外扩散的方法 - Google Patents
防止掺杂剂自源极/漏极延伸部向外扩散的方法 Download PDFInfo
- Publication number
- CN100355046C CN100355046C CNB038067633A CN03806763A CN100355046C CN 100355046 C CN100355046 C CN 100355046C CN B038067633 A CNB038067633 A CN B038067633A CN 03806763 A CN03806763 A CN 03806763A CN 100355046 C CN100355046 C CN 100355046C
- Authority
- CN
- China
- Prior art keywords
- dopant
- substrate
- oxide liners
- injected
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0221—Manufacture or treatment of FETs having insulated gates [IGFET] having asymmetry in the channel direction, e.g. lateral high-voltage MISFETs having drain offset region or extended-drain MOSFETs [EDMOS]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
- H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/031—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT]
- H10D30/0321—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon
- H10D30/0323—Manufacture or treatment of FETs having insulated gates [IGFET] of thin-film transistors [TFT] comprising silicon, e.g. amorphous silicon or polysilicon comprising monocrystalline silicon
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
- H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
- H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
- H10D30/6717—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions the source and the drain regions being asymmetrical
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/01—Manufacture or treatment
- H10D64/021—Manufacture or treatment using multiple gate spacer layers, e.g. bilayered sidewall spacers
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- High Energy & Nuclear Physics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Spectroscopy & Molecular Physics (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US10/105,522 | 2002-03-26 | ||
| US10/105,522 US6583016B1 (en) | 2002-03-26 | 2002-03-26 | Doped spacer liner for improved transistor performance |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1643672A CN1643672A (zh) | 2005-07-20 |
| CN100355046C true CN100355046C (zh) | 2007-12-12 |
Family
ID=22306307
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB038067633A Expired - Lifetime CN100355046C (zh) | 2002-03-26 | 2003-03-13 | 防止掺杂剂自源极/漏极延伸部向外扩散的方法 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US6583016B1 (enExample) |
| EP (1) | EP1488453A1 (enExample) |
| JP (1) | JP4514023B2 (enExample) |
| KR (1) | KR100948939B1 (enExample) |
| CN (1) | CN100355046C (enExample) |
| AU (1) | AU2003220198A1 (enExample) |
| TW (1) | TWI270933B (enExample) |
| WO (1) | WO2003083929A1 (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017290A (zh) * | 2015-10-20 | 2017-08-04 | 台湾积体电路制造股份有限公司 | 栅极结构、半导体器件以及形成半导体器件的方法 |
Families Citing this family (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6777298B2 (en) * | 2002-06-14 | 2004-08-17 | International Business Machines Corporation | Elevated source drain disposable spacer CMOS |
| JP4112330B2 (ja) * | 2002-10-02 | 2008-07-02 | 富士通株式会社 | 半導体装置の製造方法 |
| JP2004363443A (ja) * | 2003-06-06 | 2004-12-24 | Toshiba Corp | 不揮発性半導体記憶装置及びその製造方法 |
| US6812105B1 (en) * | 2003-07-16 | 2004-11-02 | International Business Machines Corporation | Ultra-thin channel device with raised source and drain and solid source extension doping |
| CN1296987C (zh) * | 2003-09-23 | 2007-01-24 | 茂德科技股份有限公司 | 接触孔的制造方法以及半导体元件的制造方法 |
| CN100405581C (zh) * | 2003-12-04 | 2008-07-23 | 国际商业机器公司 | 用于使用牺牲的注入层形成非无定形超薄半导体器件的方法 |
| US20070029608A1 (en) * | 2005-08-08 | 2007-02-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Offset spacers for CMOS transistors |
| KR100649311B1 (ko) * | 2005-12-15 | 2006-11-24 | 동부일렉트로닉스 주식회사 | 게이트 스페이서를 이용한 피모스 소자의 변형된 채널층형성 방법 및 이 방법에 의해 형성된 피모스 소자 |
| JP6087672B2 (ja) * | 2012-03-16 | 2017-03-01 | 株式会社半導体エネルギー研究所 | 半導体装置 |
| US9093554B2 (en) * | 2012-05-14 | 2015-07-28 | Globalfoundries Inc. | Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers |
| US10770354B2 (en) | 2017-11-15 | 2020-09-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming integrated circuit with low-k sidewall spacers for gate stacks |
| CN110265481B (zh) * | 2018-08-10 | 2023-01-17 | 友达光电股份有限公司 | 晶体管装置 |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6117719A (en) * | 1997-12-18 | 2000-09-12 | Advanced Micro Devices, Inc. | Oxide spacers as solid sources for gallium dopant introduction |
| CN1057867C (zh) * | 1995-12-20 | 2000-10-25 | 台湾茂矽电子股份有限公司 | 注入磷形成补偿的器件沟道区的半导体器件的制造方法 |
| US6235600B1 (en) * | 2000-03-20 | 2001-05-22 | Taiwan Semiconductor Manufacturing Company | Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US165659A (en) * | 1875-07-20 | Improvement in registering board-rules | ||
| US619098A (en) * | 1899-02-07 | Steam-boiler | ||
| JPH0834313B2 (ja) * | 1989-10-09 | 1996-03-29 | 株式会社東芝 | 半導体装置及びその製造方法 |
| KR950000141B1 (ko) * | 1990-04-03 | 1995-01-10 | 미쓰비시 뎅끼 가부시끼가이샤 | 반도체 장치 및 그 제조방법 |
| JPH05267327A (ja) * | 1992-03-18 | 1993-10-15 | Fujitsu Ltd | Misfet及びその製造方法 |
| JPH0823031A (ja) * | 1994-07-05 | 1996-01-23 | Oki Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JPH0897173A (ja) * | 1994-09-22 | 1996-04-12 | Sony Corp | 半導体装置の製造方法 |
| JPH08288504A (ja) * | 1995-04-14 | 1996-11-01 | Sony Corp | 半導体装置の製造方法 |
| US5756383A (en) * | 1996-12-23 | 1998-05-26 | Advanced Micro Devices | Method of manufacturing an active region of a semiconductor by diffusing a counterdopant out of a sidewall spacer |
| JPH11238882A (ja) * | 1998-02-23 | 1999-08-31 | Sony Corp | 半導体装置の製造方法 |
| JP3425079B2 (ja) * | 1998-04-24 | 2003-07-07 | 三菱電機株式会社 | 半導体装置の製造方法 |
| US6162692A (en) * | 1998-06-26 | 2000-12-19 | Advanced Micro Devices, Inc. | Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor |
| US6156598A (en) * | 1999-12-13 | 2000-12-05 | Chartered Semiconductor Manufacturing Ltd. | Method for forming a lightly doped source and drain structure using an L-shaped spacer |
| US6190982B1 (en) * | 2000-01-28 | 2001-02-20 | United Microelectronics Corp. | Method of fabricating a MOS transistor on a semiconductor wafer |
| US6346468B1 (en) * | 2000-02-11 | 2002-02-12 | Chartered Semiconductor Manufacturing Ltd. | Method for forming an L-shaped spacer using a disposable polysilicon spacer |
| JP2001291861A (ja) * | 2000-04-05 | 2001-10-19 | Nec Corp | Mosトランジスタ、トランジスタ製造方法 |
| JP2002076336A (ja) * | 2000-09-01 | 2002-03-15 | Mitsubishi Electric Corp | 半導体装置およびsoi基板 |
| WO2003054951A1 (en) * | 2001-12-19 | 2003-07-03 | Advanced Micro Devices, Inc. | Semiconductor device comprising a thin oxide liner and method of manufacturing the same |
| JP3966243B2 (ja) * | 2003-07-09 | 2007-08-29 | トヨタ自動車株式会社 | 内燃機関 |
-
2002
- 2002-03-26 US US10/105,522 patent/US6583016B1/en not_active Expired - Lifetime
-
2003
- 2003-03-13 AU AU2003220198A patent/AU2003220198A1/en not_active Abandoned
- 2003-03-13 EP EP03716494A patent/EP1488453A1/en not_active Withdrawn
- 2003-03-13 CN CNB038067633A patent/CN100355046C/zh not_active Expired - Lifetime
- 2003-03-13 KR KR1020047015039A patent/KR100948939B1/ko not_active Expired - Fee Related
- 2003-03-13 WO PCT/US2003/007559 patent/WO2003083929A1/en not_active Ceased
- 2003-03-13 JP JP2003581249A patent/JP4514023B2/ja not_active Expired - Fee Related
- 2003-03-21 TW TW092106269A patent/TWI270933B/zh not_active IP Right Cessation
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1057867C (zh) * | 1995-12-20 | 2000-10-25 | 台湾茂矽电子股份有限公司 | 注入磷形成补偿的器件沟道区的半导体器件的制造方法 |
| US6117719A (en) * | 1997-12-18 | 2000-09-12 | Advanced Micro Devices, Inc. | Oxide spacers as solid sources for gallium dopant introduction |
| US6235600B1 (en) * | 2000-03-20 | 2001-05-22 | Taiwan Semiconductor Manufacturing Company | Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107017290A (zh) * | 2015-10-20 | 2017-08-04 | 台湾积体电路制造股份有限公司 | 栅极结构、半导体器件以及形成半导体器件的方法 |
| US10749008B2 (en) | 2015-10-20 | 2020-08-18 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure, semiconductor device and the method of forming semiconductor device |
| CN107017290B (zh) * | 2015-10-20 | 2020-09-04 | 台湾积体电路制造股份有限公司 | 栅极结构、半导体器件以及形成半导体器件的方法 |
| US11195931B2 (en) | 2015-10-20 | 2021-12-07 | Taiwan Semiconductor Manufacturing Co., Ltd. | Gate structure, semiconductor device and the method of forming semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2005522033A (ja) | 2005-07-21 |
| EP1488453A1 (en) | 2004-12-22 |
| AU2003220198A1 (en) | 2003-10-13 |
| WO2003083929A1 (en) | 2003-10-09 |
| TW200305940A (en) | 2003-11-01 |
| KR20040093183A (ko) | 2004-11-04 |
| US6583016B1 (en) | 2003-06-24 |
| TWI270933B (en) | 2007-01-11 |
| KR100948939B1 (ko) | 2010-03-23 |
| CN1643672A (zh) | 2005-07-20 |
| JP4514023B2 (ja) | 2010-07-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102117748B (zh) | 双极晶体管的集电区和集电区埋层的制造方法 | |
| US6376318B1 (en) | Method of manufacturing a semiconductor device | |
| CN100355046C (zh) | 防止掺杂剂自源极/漏极延伸部向外扩散的方法 | |
| US20110156143A1 (en) | Parasitic Vertical PNP Bipolar Transistor And Its Fabrication Method In Bicmos Process | |
| JPH09504411A (ja) | セルフアラインcmosプロセス | |
| US6083798A (en) | Method of producing a metal oxide semiconductor device with raised source/drain | |
| JPH07201974A (ja) | 半導体装置の製造方法 | |
| US6913981B2 (en) | Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer | |
| US7217628B2 (en) | High performance integrated vertical transistors and method of making the same | |
| CN102117749B (zh) | 双极晶体管的集电区和集电区埋层的制造工艺方法 | |
| US6767797B2 (en) | Method of fabricating complementary self-aligned bipolar transistors | |
| US5650347A (en) | Method of manufacturing a lightly doped drain MOS transistor | |
| US6251744B1 (en) | Implant method to improve characteristics of high voltage isolation and high voltage breakdown | |
| US6642096B2 (en) | Bipolar transistor manufacturing | |
| US20040209433A1 (en) | Method for manufacturing and structure of semiconductor device with shallow trench collector contact region | |
| US6806159B2 (en) | Method for manufacturing a semiconductor device with sinker contact region | |
| US7564075B2 (en) | Semiconductor device | |
| JPH06224381A (ja) | Cmosトランジスタ用nmos低濃度ドレーンpmosハローicプロセス | |
| US7129530B2 (en) | Semiconductor device | |
| US7164186B2 (en) | Structure of semiconductor device with sinker contact region | |
| US6673703B2 (en) | Method of fabricating an integrated circuit | |
| US6624014B2 (en) | Process for fabricating a deep submicron complementary metal oxide semiconductor device having ultra shallow junctions | |
| US7781295B1 (en) | System and method for providing a single deposition emitter/base in a bipolar junction transistor | |
| KR880002271A (ko) | Vlsi 자기-정합식 바이폴라 트랜지스터 | |
| CN102543727A (zh) | 锗硅hbt结构、其赝埋层结构及其制造方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CI01 | Publication of corrected invention patent application |
Correction item: Inventor Correct: Ye Bingjin False: Zhong Bingjin Number: 29 Volume: 21 |
|
| CI02 | Correction of invention patent application |
Correction item: Inventor Correct: Ye Bingjin False: Zhong Bingjin Number: 29 Page: The title page Volume: 21 |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: INVENTOR; FROM: ZHONG BINGJIN TO: YE BINGJIN |
|
| ERR | Gazette correction |
Free format text: CORRECT: INVENTOR; FROM: ZHONG BINGJIN TO: YE BINGJIN |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: ADVANCED MICRO DEVICES INC Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC. Effective date: 20100708 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA, USA TO: GRAND CAYMAN ISLAND RITISH CAYMAN ISLANDS |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20100708 Address after: Grand Cayman, Cayman Islands Patentee after: GLOBALFOUNDRIES Inc. Address before: California, USA Patentee before: ADVANCED MICRO DEVICES, Inc. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20210308 Address after: California, USA Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd. Address before: Greater Cayman Islands, British Cayman Islands Patentee before: GLOBALFOUNDRIES Inc. |
|
| CX01 | Expiry of patent term |
Granted publication date: 20071212 |
|
| CX01 | Expiry of patent term |