CN1643672A - 使用氧化硅衬垫的离子注入以防止掺杂剂自源极/漏极延伸部向外扩散的方法 - Google Patents

使用氧化硅衬垫的离子注入以防止掺杂剂自源极/漏极延伸部向外扩散的方法 Download PDF

Info

Publication number
CN1643672A
CN1643672A CNA038067633A CN03806763A CN1643672A CN 1643672 A CN1643672 A CN 1643672A CN A038067633 A CNA038067633 A CN A038067633A CN 03806763 A CN03806763 A CN 03806763A CN 1643672 A CN1643672 A CN 1643672A
Authority
CN
China
Prior art keywords
ion
dopant
substrate
oxide liners
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA038067633A
Other languages
English (en)
Other versions
CN100355046C (zh
Inventor
A·C·韦
M·B·菲赛利耶
中秉津
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries US Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN1643672A publication Critical patent/CN1643672A/zh
Application granted granted Critical
Publication of CN100355046C publication Critical patent/CN100355046C/zh
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
    • H01L21/2652—Through-implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/2658—Bombardment with radiation with high-energy radiation producing ion implantation of a molecular ion, e.g. decaborane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/6656—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using multiple spacer layers, e.g. multiple sidewall spacers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66659—Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
    • H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
    • H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
    • H01L29/78624—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile the source and the drain regions being asymmetrical

Abstract

提供一种改善晶体管性能的半导体器件的制造方法，该半导体器件的制造是通过离子注入(31)将掺杂剂注入氧化物衬垫(30)以防止或充分减少掺杂剂自源极/漏极的浅层延伸部(23)扩散出来。具体实施例包含离子注入P型掺杂剂，例如B或BF2，使用栅极电极(21)作为掩膜，形成源极/漏极的浅层延伸部(23)，沉积共形的氧化物衬垫(30)，并以基本上与源极/漏极的浅层延伸部(23)相同的掺杂剂浓度，通过离子注入(31)将P型杂质注入氧化物衬垫(30)。后续工艺包含沉积间隔层，进行蚀刻形成侧壁间隔(40)，进行离子注入形成深层中等或高浓度的源极/漏极注入物(41)，以及激活退火(activation annealing)。

Description

使用氧化硅衬垫的离子注入以防止掺杂剂自源极/漏极延伸部向 外扩散的方法
技术领域
本发明涉及改善晶体管性能的半导体器件以及可行方法。本发明特别适合应用于制造具有深亚微米设计特征以及浅结深的高速集成电路的高密度半导体器件。
背景技术
由于对高密度和高性能需求的增加，在半导体制造技术上也需要更严格的要求，特别是晶体管性能与高操作速度的提升。晶体管性能是由许多不同的因素决定，且容易在制造过程中受到不同操作影响而降低，例如，会使衬底暴露在高温和等离子气氛下的等离子沉积技术，如在等离子增强的化学气相沉积的过程中。由于对于高操作速度的需求因而需要使用具有相对低介电常数的介电材料，介电常数例如约3.9或以下。文中所示的介电常数(K)是以真空下为1作为基准。
如图1所示，在实施传统的制造技术时，通常栅极电极11形成在半导体衬底10上，该栅极电极11与该衬底10之间形成有栅极介电层12，如栅极氧化层。接着，进行离子注入，以注入源极/漏极的浅层延伸部13。然后，在栅极电极11的侧表面和衬底10的上表面形成厚度约50埃至约200埃的氧化物衬垫15，其在后续形成侧壁间隔16的蚀刻过程保护该衬底表面，该侧壁间隔通常由氮化硅形成。参考符号14说明中等或高浓度掺杂的源极/漏极区域，通常在形成侧壁间隔16之后注入。
在实行例如用以形成图1所示的结构的传统半导体制造技术时会遭遇困难。例如通过低压化学气相沉积形成氧化硅衬垫15的沉积过程的高温工艺中，其温度通常为约700℃或更高，注入源极/漏极区域13的掺杂杂质会扩散并分离至氧化物衬垫15中，该掺杂杂质的实例包括P型杂质，如硼(B)以及二氟化硼(BF2)。400℃的低温CVD衬垫氧化物可用于防止此种扩散以及掺杂剂的减损。然而，在激活退火所需的高温过程中，例如高于100℃的温度历时5至10秒，也会发生掺杂剂的减损。此种自源极/漏极延伸部扩散的减损是不利的，如增加该源极/漏极延伸部的电阻。以往，用以解决此项问题的方法包括，以高于所需的注入剂量，离子注入掺杂杂质，例如B或BF2，以抵销掺杂剂扩散所造成的减损。然而，此种方法将不利地导致较深的结深(Xj)，而无法符合朝向小型化发展的持续性需求。
发明内容
本发明的优点是提供一种具有改善性能的晶体管的高密度半导体器件的制造方法。
本发明的其它优点与特征将揭示在后文的说明书中，本领域技术人员可根据试验轻易地了解，或通过实行本发明而获知这些优点与特征。由所附的权利要求所记载的内容也可了解或获知本发明的优点。
根据本发明的一个方面，前述及其它优点均可通过半导体器件的制造方法加以达成，该方法包括：在衬底的上表面形成具有侧表面的栅极电极，且该衬底与该栅极电极之间覆盖有栅极介电层；使用栅极电极作为掩膜，通过离子注入将掺杂剂注入衬底，形成源极/漏极的浅层延伸部；在该栅极电极的侧表面与该衬底的上表面形成氧化物衬垫；以及通过离子注入将掺杂剂注入该氧化物衬垫。
本发明的具体实施例包含：通过离子注入将B或BF2注入衬底，形成具有第一杂质浓度的源极/漏极的浅层延伸部；在栅极电极的上表面、侧表面以及该衬底的上表面沉积共形的氧化物衬垫；通过离子注入将B或BF2注入氧化物衬垫，使其实质上与源极/漏极的浅层延伸部具有相同的杂质浓度，例如约1×1020至约6×1020个原子/立方厘米；沉积间隔层，例如氮化硅或氧氮化硅；以及进行蚀刻形成侧壁间隔。接着，可以去除栅极电极上表面上的氧化物衬垫部分。在去除栅极电极上表面的氧化物衬垫部分之前或之后，进行离子注入形成深层中等或高浓度的掺杂源极/漏极区域。随后，可进行激活退火。
本领域技术人员由后文的详细叙述中可以轻易地了解本发明的其它优点与观点，其中仅揭示较佳的具体实施例，以简洁的方法说明施行本发明的最佳模式。应了解，本发明也可通过其它不同的具体实施例加以施行，其各项细节也可基于不同观点在不脱离本发明的情况下进行修改。此外，图式与说明书本身仅是用于说明，而非用于限制本发明。
附图说明
图1是由传统晶体管制造技术所造成掺杂剂扩散出来的示意图；
图2至图4是根据本发明具体实施例的方法的各个步骤的示意图；
图5至图8是本发明另一方面的各个阶段的示意图。
在图2至图4以及图5至图8中，类似的特征或组件由类似的参考符号表示。
具体实施方式
本发明针对高密度以及小型化的高可靠性半导体器件仍有持续性需求。本发明通过创建屏障来防止杂质自源极/漏极的浅层延伸部扩散至氧化物衬垫，提供一种改善晶体管性能的半导体器件以及可行的方法。本发明中，用以达成该项目的的具体实施例是通过离子注入将杂质注入氧化物衬垫。因此，本发明提供一种方法，该方法可以避免或明显减少杂质(例如，P型杂质，如B以及BF2)扩散出来，同时，使浅的结深(Xj)维持在约200埃至约300埃。
本发明的具体实施例包括：在半导体衬底上形成栅极电极，且该衬底与该栅极电极之间覆盖有栅极介电层，使用栅极电极作为掩膜，通过离子注入将掺杂剂(例如，BF2)注入衬底，形成浅的源极/漏极区域。此种离子注入可以使用传统的方法进行，例如在注入剂量约5×1014至约2×1015个离子/平方厘米和注入能量约1至约3 KeV的条件下离子注入BF2，通常所形成的杂质浓度约为1×1020至约6×1020个原子/立方厘米。
接着，在栅极电极的上表面、侧表面以及衬底的上表面沉积氧化物衬垫，该氧化物衬垫的厚度为约50埃至约200埃。然后进行离子注入，在实质上与形成源极/漏极的浅层延伸部所使用的相同条件下，例如注入剂量约5×1014至约2×1015个离子/平方厘米以及注入能量约1至约3KeV的条件，将BF2杂质注入氧化物衬垫，由此形成杂质浓度约为1×1020至约6×1020个原子/立方厘米的氧化物衬垫。
接着，沉积厚度约600埃至约1200埃的间隔层，例如氮化硅或氮氧化硅。然后进行各向异性的蚀刻形成侧壁间隔。接着进行BF2的离子注入，形成相对深层的中等或高浓度的源极/漏极注入层。在形成相对深层的中等或高浓度的源极/漏极注入层的离子注入之前或之后，可利用氢氟酸去除栅极电极上表面上的氧化硅衬垫部分。然后，进行激活退火。将掺杂杂质注入氧化硅衬垫可增加扩散阻碍，进而防止或明显地减少后续工艺中，例如间隔层的沉积以及激活退火的期间，杂质自浅的源极/漏极区域扩散出来。
本发明的具体实施例显示在图2至图4中，其中类似的特征或组件由类似的参考符号与数字表示。如图2所示，栅极电极21(通常是掺杂的多晶)形成在衬底20(通常是掺杂的单晶硅)或外延层上，该外延层(epitaxial layer)形成在半导体衬底或井区域上。使用栅极电极21作为掩膜，以离子注入将杂质(例如，BF2)注入衬底20，形成源极/漏极的浅层延伸部23。接着，如图3所示，在栅极电极21的上表面与侧表面以及衬底20的上表面沉积氧化物衬垫30，该氧化物衬垫30的厚度为约50埃至约200埃。然后进行离子注入，如图3中的箭号31所示，将BF2杂质注入氧化物衬垫30，使其与源极/漏极的浅层延伸部23的注入有实质相同的浓度，藉此增加BF2原子自该源极/漏极的浅层延伸部23扩散出来的阻碍。
随后，沉积间隔材料层并进行各向异性蚀刻，形成侧壁间隔40，如图4所示，侧壁间隔40在衬底表面的厚度通常约600埃至约1200埃。在形成侧壁间隔40的蚀刻过程中，氧化硅层30作为蚀刻终止层，故可避免损及衬底20。后续工艺包含：利用如氢氟酸去除栅极电极21与衬底20上表面的氧化硅衬垫30。在去除栅极电极21与衬底上表面的硅或氧化硅层40部分前或去除后进行离子注入，形成深层的中等或高浓度掺杂的源极/漏极区域(41)，形成如图4所示的结构。
本发明的另一方面包括能够选择性优化双层埋入式氧化层BOX(dual buried oxide)的绝缘体上硅SOI(silicon-on-insulative)结构中的源极与漏极区域厚度的方法。此种方法显示在图5至图8，其中类似的特征或组件由类似的参考符号表示。如图5所示，双层BOX结构包括由硅50、BOX 51、硅层52、BOX 53、以及硅层54所成的衬底。栅极电极55形成在双层BOX衬底上，且栅极电极55与衬底之间形成有栅极介电层56，侧壁间隔57形成在栅极电极55的侧表面上。
如图6所示，接着在该结构的源极侧边上形成光刻胶掩膜60。如图7所示，接着进行蚀刻自漏极边去除顶部的硅层54以及上层的BOX层53。接着，如图8所示，从下层的硅层52外延生长硅54A(expitaxiallygrown)。在此方法中，可独立于源极区域54B形成较深的漏极区域54A。
本发明能够制造表现出改善的晶体管性能以及例如约200埃至约300埃的浅结深(Xj)的半导体器件。将杂质注入氧化物衬垫，该注入的杂质与源极/漏极的浅层延伸部属相同类型且具有实质相同的浓度，因而可以防止或实质减少杂质自源极/漏极的浅层延伸部扩散出来，进而改善源极/漏极的延伸部的电阻，同时明显地改善晶体管性能，符合小型化的持续需求。
本发明有利于应用在产业上，制造各种不同类型的半导体器件。本发明特别有利于在产业上，制造约0.12微米设计规则的高密度半导体器件。
前述内容中已具体揭示多项细节，例如特定材料、结构、反应物、工艺等，以使本发明获得更详尽的说明；但本发明的施行并非仅局限于前述的特定细节。在其它实例中，为使本发明的精神更臻明确，并未针对已知工艺中的材料与技术加以描述。
在本发明的说明书中，仅揭示本发明的较佳具体实施例及其用途的数个实例。应了解的是，本发明可用于其它不同组合以及环境，也可在本发明的精神范畴下进行变更与修改。

Claims (10)

1.一种半导体器件的制造方法，包括下列步骤：
在衬底(20)上表面上形成具有侧表面的栅极电极(21)，在该衬底(20)与该栅极电极(21)之间有栅极介电层(22)；
通过离子注入将掺杂剂注入衬底，并使用栅极电极(21)作为掩膜，形成源极/漏极的浅层延伸部(23)；
在该栅极电极(21)的侧表面与该衬底(20)的上表面上形成氧化物衬垫(30)；以及
通过离子注入(31)将掺杂剂注入该氧化物衬垫(30)。
2.如权利要求1的方法，还包括：
在该氧化物衬垫(30)上沉积间隔材料层；
进行蚀刻，在该氧化物衬垫(30)上形成侧壁间隔(40)；
通过离子注入将掺杂剂注入该衬底，形成深层中等或高浓度的掺杂注入物(41)；以及
激活退火。
3.如权利要求2的方法，包括：
形成包括氧化硅的氧化物衬垫(30)；以及
形成包括氮化硅或氮氧化硅的间隔层(40)。
4.如权利要求3的方法，包括离子注入(31)P型杂质作为掺杂剂。
5.如权利要求4的方法，包括离子注入(31)硼(B)或二氟化硼(BF2)作为掺杂剂。
6.如权利要求2的方法，包括：
通过离子注入将掺杂剂注入该衬底，形成第一杂质浓度的源极/漏极的浅层延伸部(23)；以及
通过离子注入将掺杂剂注入该氧化物衬垫(30)，该氧化物衬垫(30)中的杂质浓度实质上与第一杂质浓度相同。
7.如权利要求6的方法，包括通过离子注入将掺杂质注入衬底形成源极/漏极的浅层延伸部(23)，以及将掺杂剂注入氧化物衬垫(30)，该注入的掺杂剂浓度约为1×1020至约2×1020个原子/立方厘米。
8.如权利要求2的方法，包括通过离子注入(31)将掺杂杂质注入氧化物衬垫(30)，使该氧化物衬垫(30)的掺杂剂浓度约为1原子百分比。
9.如权利要求5的方法，包括通过离子注入(31)将BF2注入氧化物衬垫(30)，注入剂量约5×1014至约2×1015个离子/平方厘米以及注入能量约1至约3KeV。
10.如权利要求1的方法，包括形成厚度约50埃至约200埃的氧化物衬垫(30)。
CNB038067633A 2002-03-26 2003-03-13 防止掺杂剂自源极/漏极延伸部向外扩散的方法 Expired - Lifetime CN100355046C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/105,522 2002-03-26
US10/105,522 US6583016B1 (en) 2002-03-26 2002-03-26 Doped spacer liner for improved transistor performance

Publications (2)

Publication Number Publication Date
CN1643672A true CN1643672A (zh) 2005-07-20
CN100355046C CN100355046C (zh) 2007-12-12

Family

ID=22306307

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038067633A Expired - Lifetime CN100355046C (zh) 2002-03-26 2003-03-13 防止掺杂剂自源极/漏极延伸部向外扩散的方法

Country Status (8)

Country Link
US (1) US6583016B1 (zh)
EP (1) EP1488453A1 (zh)
JP (1) JP4514023B2 (zh)
KR (1) KR100948939B1 (zh)
CN (1) CN100355046C (zh)
AU (1) AU2003220198A1 (zh)
TW (1) TWI270933B (zh)
WO (1) WO2003083929A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110265481A (zh) * 2018-08-10 2019-09-20 友达光电股份有限公司 晶体管装置

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6777298B2 (en) * 2002-06-14 2004-08-17 International Business Machines Corporation Elevated source drain disposable spacer CMOS
JP4112330B2 (ja) * 2002-10-02 2008-07-02 富士通株式会社 半導体装置の製造方法
JP2004363443A (ja) * 2003-06-06 2004-12-24 Toshiba Corp 不揮発性半導体記憶装置及びその製造方法
US6812105B1 (en) 2003-07-16 2004-11-02 International Business Machines Corporation Ultra-thin channel device with raised source and drain and solid source extension doping
CN1296987C (zh) * 2003-09-23 2007-01-24 茂德科技股份有限公司 接触孔的制造方法以及半导体元件的制造方法
EP1695381A4 (en) * 2003-12-04 2008-09-17 Ibm METHOD FOR FORMING NON-AMORPHOUS, ULTRA-FINE DEVICES USING SACRIFICIAL IMPLANTATION LAYER
US20070029608A1 (en) * 2005-08-08 2007-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Offset spacers for CMOS transistors
KR100649311B1 (ko) * 2005-12-15 2006-11-24 동부일렉트로닉스 주식회사 게이트 스페이서를 이용한 피모스 소자의 변형된 채널층형성 방법 및 이 방법에 의해 형성된 피모스 소자
JP6087672B2 (ja) * 2012-03-16 2017-03-01 株式会社半導体エネルギー研究所 半導体装置
US9093554B2 (en) * 2012-05-14 2015-07-28 Globalfoundries Inc. Methods of forming semiconductor devices with embedded semiconductor material as source/drain regions using a reduced number of spacers
US10141417B2 (en) * 2015-10-20 2018-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Gate structure, semiconductor device and the method of forming semiconductor device
US10770354B2 (en) 2017-11-15 2020-09-08 Taiwan Semiconductor Manufacturing Co., Ltd. Method of forming integrated circuit with low-k sidewall spacers for gate stacks

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US619098A (en) * 1899-02-07 Steam-boiler
US165659A (en) * 1875-07-20 Improvement in registering board-rules
JPH0834313B2 (ja) * 1989-10-09 1996-03-29 株式会社東芝 半導体装置及びその製造方法
KR950000141B1 (ko) * 1990-04-03 1995-01-10 미쓰비시 뎅끼 가부시끼가이샤 반도체 장치 및 그 제조방법
JPH05267327A (ja) * 1992-03-18 1993-10-15 Fujitsu Ltd Ｍｉｓｆｅｔ及びその製造方法
JPH0823031A (ja) * 1994-07-05 1996-01-23 Oki Electric Ind Co Ltd 半導体装置及びその製造方法
JPH0897173A (ja) * 1994-09-22 1996-04-12 Sony Corp 半導体装置の製造方法
JPH08288504A (ja) * 1995-04-14 1996-11-01 Sony Corp 半導体装置の製造方法
CN1057867C (zh) * 1995-12-20 2000-10-25 台湾茂矽电子股份有限公司 注入磷形成补偿的器件沟道区的半导体器件的制造方法
US5756383A (en) * 1996-12-23 1998-05-26 Advanced Micro Devices Method of manufacturing an active region of a semiconductor by diffusing a counterdopant out of a sidewall spacer
US6117719A (en) * 1997-12-18 2000-09-12 Advanced Micro Devices, Inc. Oxide spacers as solid sources for gallium dopant introduction
JPH11238882A (ja) * 1998-02-23 1999-08-31 Sony Corp 半導体装置の製造方法
JP3425079B2 (ja) * 1998-04-24 2003-07-07 三菱電機株式会社 半導体装置の製造方法
US6162692A (en) * 1998-06-26 2000-12-19 Advanced Micro Devices, Inc. Integration of a diffusion barrier layer and a counter dopant region to maintain the dopant level within the junctions of a transistor
US6156598A (en) * 1999-12-13 2000-12-05 Chartered Semiconductor Manufacturing Ltd. Method for forming a lightly doped source and drain structure using an L-shaped spacer
US6190982B1 (en) * 2000-01-28 2001-02-20 United Microelectronics Corp. Method of fabricating a MOS transistor on a semiconductor wafer
US6346468B1 (en) * 2000-02-11 2002-02-12 Chartered Semiconductor Manufacturing Ltd. Method for forming an L-shaped spacer using a disposable polysilicon spacer
US6235600B1 (en) * 2000-03-20 2001-05-22 Taiwan Semiconductor Manufacturing Company Method for improving hot carrier lifetime via a nitrogen implantation procedure performed before or after a teos liner deposition
JP2001291861A (ja) * 2000-04-05 2001-10-19 Nec Corp Ｍｏｓトランジスタ、トランジスタ製造方法
JP2002076336A (ja) * 2000-09-01 2002-03-15 Mitsubishi Electric Corp 半導体装置およびｓｏｉ基板
AU2002358269A1 (en) * 2001-12-19 2003-07-09 Advanced Micro Devices, Inc. Semiconductor device comprising a thin oxide liner and method of manufacturing the same
JP3966243B2 (ja) * 2003-07-09 2007-08-29 トヨタ自動車株式会社 内燃機関

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110265481A (zh) * 2018-08-10 2019-09-20 友达光电股份有限公司 晶体管装置

Also Published As

Publication number Publication date
KR100948939B1 (ko) 2010-03-23
KR20040093183A (ko) 2004-11-04
TW200305940A (en) 2003-11-01
TWI270933B (en) 2007-01-11
US6583016B1 (en) 2003-06-24
AU2003220198A1 (en) 2003-10-13
JP2005522033A (ja) 2005-07-21
EP1488453A1 (en) 2004-12-22
WO2003083929A1 (en) 2003-10-09
CN100355046C (zh) 2007-12-12
JP4514023B2 (ja) 2010-07-28

Similar Documents

Publication Publication Date Title
CN100355046C (zh) 防止掺杂剂自源极/漏极延伸部向外扩散的方法
US6387782B2 (en) Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer
CN101044611A (zh) 用于制造具有蚀刻终止层的绝缘体上硅（soi）晶片的方法
CN1720607A (zh) 含有掺杂高－k侧壁隔片的场效应晶体管的漏极/源极延伸结构
JP2957757B2 (ja) トランジスタ製作方法
EP0797840B1 (en) Use of oblique implantation in forming base of bipolar transistor
JPH09504411A (ja) セルフアラインｃｍｏｓプロセス
US6083798A (en) Method of producing a metal oxide semiconductor device with raised source/drain
US5217924A (en) Method for forming shallow junctions with a low resistivity silicide layer
US6593640B1 (en) Bipolar transistor and methods of forming bipolar transistors
US6683356B2 (en) Semiconductor device with oxygen doped regions
US5650347A (en) Method of manufacturing a lightly doped drain MOS transistor
US7572708B1 (en) Utilization of doped glass on the sidewall of the emitter window in a bipolar transistor structure
US20040209433A1 (en) Method for manufacturing and structure of semiconductor device with shallow trench collector contact region
US20030062598A1 (en) Method for manufacturing and structure of semiconductor device with sinker contact region
US20050179060A1 (en) Semiconductor device for integrated injection logic cell and process for fabricating the same
US6673703B2 (en) Method of fabricating an integrated circuit
US7164186B2 (en) Structure of semiconductor device with sinker contact region
US6624014B2 (en) Process for fabricating a deep submicron complementary metal oxide semiconductor device having ultra shallow junctions
KR100312383B1 (ko) 반도체 소자의 트랜지스터 형성방법
CN101989549B (zh) Nmos晶体管的制造方法
JP2527628B2 (ja) 半導体装置の製造方法
US6495432B2 (en) Method of improving a dual gate CMOS transistor to resist the boron-penetrating effect
US6362061B1 (en) Method to differentiate source/drain doping by using oxide slivers
CN102543727A (zh) 锗硅hbt结构、其赝埋层结构及其制造方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
CI01 Publication of corrected invention patent application

Correction item: Inventor

Correct: Ye Bingjin

False: Zhong Bingjin

Number: 29

Volume: 21

CI02 Correction of invention patent application

Correction item: Inventor

Correct: Ye Bingjin

False: Zhong Bingjin

Number: 29

Page: The title page

Volume: 21

COR Change of bibliographic data

Free format text: CORRECT: INVENTOR; FROM: ZHONG BINGJIN TO: YE BINGJIN

ERR Gazette correction

Free format text: CORRECT: INVENTOR; FROM: ZHONG BINGJIN TO: YE BINGJIN

C14 Grant of patent or utility model
GR01 Patent grant
ASS Succession or assignment of patent right

Owner name: ADVANCED MICRO DEVICES INC

Free format text: FORMER OWNER: ADVANCED MICRO DEVICES INC.

Effective date: 20100708

C41 Transfer of patent application or patent right or utility model
COR Change of bibliographic data

Free format text: CORRECT: ADDRESS; FROM: CALIFORNIA, USA TO: GRAND CAYMAN ISLAND RITISH CAYMAN ISLANDS

TR01 Transfer of patent right

Effective date of registration: 20100708

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES Inc.

Address before: California, USA

Patentee before: ADVANCED MICRO DEVICES, Inc.

TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20210308

Address after: California, USA

Patentee after: Lattice chip (USA) integrated circuit technology Co.,Ltd.

Address before: Greater Cayman Islands, British Cayman Islands

Patentee before: GLOBALFOUNDRIES Inc.

CX01 Expiry of patent term

Granted publication date: 20071212

CX01 Expiry of patent term