JP2005101312A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2005101312A
JP2005101312A JP2003333620A JP2003333620A JP2005101312A JP 2005101312 A JP2005101312 A JP 2005101312A JP 2003333620 A JP2003333620 A JP 2003333620A JP 2003333620 A JP2003333620 A JP 2003333620A JP 2005101312 A JP2005101312 A JP 2005101312A
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JP
Japan
Prior art keywords
chip
adhesive
mounting substrate
semiconductor device
mask
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003333620A
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English (en)
Japanese (ja)
Other versions
JP2005101312A5 (https=
Inventor
Tomoko Tono
朋子 東野
Kazunari Suzuki
一成 鈴木
Toshihiro Shiotsuki
敏弘 塩月
Hideyuki Suga
秀幸 須賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp, Renesas Eastern Japan Semiconductor Inc filed Critical Renesas Technology Corp
Priority to JP2003333620A priority Critical patent/JP2005101312A/ja
Publication of JP2005101312A publication Critical patent/JP2005101312A/ja
Publication of JP2005101312A5 publication Critical patent/JP2005101312A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

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  • Die Bonding (AREA)
JP2003333620A 2003-09-25 2003-09-25 半導体装置の製造方法 Pending JP2005101312A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003333620A JP2005101312A (ja) 2003-09-25 2003-09-25 半導体装置の製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003333620A JP2005101312A (ja) 2003-09-25 2003-09-25 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2005101312A true JP2005101312A (ja) 2005-04-14
JP2005101312A5 JP2005101312A5 (https=) 2006-11-09

Family

ID=34461576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003333620A Pending JP2005101312A (ja) 2003-09-25 2003-09-25 半導体装置の製造方法

Country Status (1)

Country Link
JP (1) JP2005101312A (https=)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008509572A (ja) * 2004-08-13 2008-03-27 インテル コーポレイション スタックダイパッケージにおいてダイを取り付ける方法及び装置
JP2011135102A (ja) * 2011-03-23 2011-07-07 Renesas Electronics Corp 半導体装置
JP2012015554A (ja) * 2011-10-17 2012-01-19 Renesas Electronics Corp 半導体装置の製造方法、および積層型半導体装置の製造方法
US9252126B2 (en) 2012-04-02 2016-02-02 Ps4 Luxco S.A.R.L. Multi Chip Package-type semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01253244A (ja) * 1988-04-01 1989-10-09 Toshiba Chem Corp 半導体装置の製造方法
JPH02177553A (ja) * 1988-12-28 1990-07-10 Matsushita Electric Ind Co Ltd 集積回路装置およびその製造方法
JP2001338932A (ja) * 2000-05-29 2001-12-07 Canon Inc 半導体装置及び半導体装置の製造方法
JP2003264205A (ja) * 2002-03-08 2003-09-19 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01253244A (ja) * 1988-04-01 1989-10-09 Toshiba Chem Corp 半導体装置の製造方法
JPH02177553A (ja) * 1988-12-28 1990-07-10 Matsushita Electric Ind Co Ltd 集積回路装置およびその製造方法
JP2001338932A (ja) * 2000-05-29 2001-12-07 Canon Inc 半導体装置及び半導体装置の製造方法
JP2003264205A (ja) * 2002-03-08 2003-09-19 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008509572A (ja) * 2004-08-13 2008-03-27 インテル コーポレイション スタックダイパッケージにおいてダイを取り付ける方法及び装置
JP2011135102A (ja) * 2011-03-23 2011-07-07 Renesas Electronics Corp 半導体装置
JP2012015554A (ja) * 2011-10-17 2012-01-19 Renesas Electronics Corp 半導体装置の製造方法、および積層型半導体装置の製造方法
US9252126B2 (en) 2012-04-02 2016-02-02 Ps4 Luxco S.A.R.L. Multi Chip Package-type semiconductor device

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