JP2011135102A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP2011135102A JP2011135102A JP2011063771A JP2011063771A JP2011135102A JP 2011135102 A JP2011135102 A JP 2011135102A JP 2011063771 A JP2011063771 A JP 2011063771A JP 2011063771 A JP2011063771 A JP 2011063771A JP 2011135102 A JP2011135102 A JP 2011135102A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chip
- adhesive layer
- semiconductor
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/27—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L24/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
- H01L2224/743—Apparatus for manufacturing layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01019—Potassium [K]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01074—Tungsten [W]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01075—Rhenium [Re]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01077—Iridium [Ir]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Die Bonding (AREA)
Abstract
【解決手段】半導体ウエハ1Wの半導体基板1Sの内部に集光点を合わせた状態でレーザ光を照射することにより改質領域PLを形成する。続いて、半導体ウエハ1Wの裏面に回転塗布法により液状の接着材を塗布した後、これを乾燥させて固体状の接着層8aを形成する。その後、上記改質領域PLを分割起点として半導体ウエハ1Wを個々の半導体チップに分割する。この半導体チップをその裏面の接着層8aにより他の半導体チップの主面上に接着することにより、半導体チップが多段に積層された構成を有する半導体装置を製造する。
【選択図】図13
Description
本実施の形態1の半導体装置の製造方法を図1のフロー図に沿って説明する。
本実施の形態2では、前記実施の形態1と同様に、図1の前工程100からレーザ照射工程102B1を経た後、チップ分割工程102Bの接着層形成工程102B2において、ウエハの裏面に印刷法により接着層を形成する。
前記実施の形態1,2では、チップ分割工程において、改質領域LBを形成するためのレーザ照射工程後に、ウエハ1Wの裏面に接着層を形成する場合について説明した。本実施の形態3では、チップ分割工程において、ウエハ1Wの裏面に接着層を形成した後、、改質領域LBを形成するためのレーザ照射工程を行う場合について説明する。
本実施の形態4では、前記実施の形態3と同様に、図36の前工程200から裏面研磨工程202A3を経た後、チップ分割工程202Bの接着層形成工程202B1において、ウエハ1Wの裏面に印刷法により接着層を形成する。
本実施の形態5では、ウエハの裏面に印刷法により接着層を形成する場合の変形例について説明する。
図55は本実施の形態6の半導体装置の断面図を示している。本実施の形態6では、下層のチップ18Cが、その主面(デバイス形成面)を配線基板17の主面に向けた状態で、バンプ電極30を介して配線基板17の主面上に実装されている。チップ18Cの集積回路は、バンプ電極30を通じて配線基板17の主面上の電極に電気的に接続され、さらに配線基板17の配線に電気的に接続されている。バンプ電極30は、例えば鉛(Pb)−錫(Sn)半田により形成されている。チップ18Cと配線基板17との対向面間にはアンダーフィル31が充填されている。
図56は本実施の形態7の半導体装置の断面図を示している。本実施の形態7では、チップ1C1(1C)の主面上に、他のチップ1C2(1C)がその主面を上に向けた状態で実装されている。最上層のチップ1C2の裏面は接着層8aを介してチップ1C1の主面に接着されている。チップ1C2の主面の集積回路はワイヤ21を介して配線基板17の電極17aに電気的に接続されている。チップ1C1,1C2の裏面の接着層8aは薄く形成されているので、チップ18C,1C1,1C2の多段構成を有する半導体装置を薄型にすることができる。また、最上層のチップ1C2の裏面の接着層8aの厚さは、中間層のチップ1C1の裏面の接着層8aの厚さと等しい。各チップ1C1,1C2の裏面の接着層8aの厚さを等しくすることにより、各チップ1C1,1C2の裏面の接着層8aの厚さ設計を容易にすることができる。
図57は本実施の形態8の半導体装置の断面図を示している。本実施の形態8の半導体装置は、1つのパッケージ内に所望の機能のシステムが構築されたSIP(System In Package)とされている。配線基板17の主面上には、複数の薄型のチップ18,1C,37Cが積層されている。最下層のチップ18Cは、その主面のバンプ電極30を介して配線基板17の主面上に実装されている。このチップ18Cの主面には、例えばCPU(Central Processing Unit)やDSP(Digital Signal Processor)等のような論理回路が形成されている。このチップ18Cの裏面上には、接着層8aを介してチップ1Cが実装されている。このチップ1Cの主面には、例えばSRAM(Static Random Access Memory)やフラッシュメモリ等のようなメモリ回路が形成されている。このチップ1Cの主面のパッド1LBは、ワイヤ21を介して配線基板17の主面の電極17aと電気的に接続されている。このチップ1Cの主面上には、スペーサ35およびDAF36を介してチップ37Cが実装されている。このチップ37Cには、例えばSRAMやフラッシュメモリ等のようなメモリ回路が形成されており、チップ37Cの主面のパッドは、ワイヤ21を介して配線基板17の主面の電極17aと電気的に接続されている。このようなチップ18C,1C,37Cおよびワイヤ21は封止体22により封止されている。
明は上記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可
能であることは言うまでもない。
1C 半導体チップ(第2チップ)
1S 半導体基板
1L 配線層
1Li,1Li1,1Li2,1Li3 層間絶縁膜
1LB ボンディングパッド
1LBt テスト用のボンディングパッド
1Lp 表面保護膜
2 開口部
3 接着層
4 支持基板
4a 剥離層
5 レーザ発生部
7 ノズル
8 接着材
8a,8b,8c 接着層
10 治具
10a テープ
10b リング
11 レーザ発生部
12 載置台
15 載置台
17 配線基板
17a,17b 電極
18C 半導体チップ(第1チップ)
18S 半導体基板
18L 配線層
18LB ボンディングパッド
20a 接着層
21 ボンディングワイヤ
22 封止体
23 はんだボール
25A,25B マスク
25A1,25B1 開口部
25A2,25B2 マスクパターン
26 スキージ
30 バンプ電極
31 アンダーフィル
35 スペーサ
36 DAF
37C 半導体チップ
CR 切断領域
CL 切断線
Am アライメントターゲット
LB1 レーザ光
LB2 レーザ光
PL 改質領域
Claims (4)
- 上面、前記上面に形成された複数の配線、前記上面に形成された複数の第1電極、前記上面とは反対側の下面、および前記下面に形成された複数の第2電極を有する配線基板と、
第1表面、前記第1表面に形成された複数の第1ボンディングパッド、および前記第1表面とは反対側の第1裏面を有し、前記第1裏面が前記上面と対向するように、第1接着層を介して前記配線基板の前記上面上に搭載された第1半導体チップと、
第2表面、前記第2表面に形成された複数の第2ボンディングパッド、および前記第2表面とは反対側の第2裏面を有し、前記第2裏面が前記第1表面と対向するように、第2接着層を介して前記第1半導体チップの前記第1表面上に搭載された第2半導体チップと、
前記第1半導体チップおよび前記第2半導体チップを封止する封止体と、
前記複数の第2電極上に形成された複数の外部端子と、
を含み、
前記第2接着層のうちの前記第2半導体チップと平面的に重なる部分の厚さは、前記第1接着層のうちの前記第1半導体チップと平面的に重なる部分の厚さよりも薄いことを特徴とする半導体装置。 - 請求項1において、
前記配線基板の前記上面の粗さは、前記第1半導体チップの前記第1表面の粗さよりも大きく、
前記第1表面の粗さは、前記第2接着層のうちの前記第2半導体チップと平面的に重なる部分の厚さよりも小さいことを特徴とする半導体装置。 - 請求項2において、
前記第1接着層は、フィルム基板を有しており、
前記第2接着層は、前記フィルム基板を有していないことを特徴とする半導体装置。 - 請求項3において、
前記第2接着層は、スピンコート法により形成されることを特徴とする半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011063771A JP5297491B2 (ja) | 2011-03-23 | 2011-03-23 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2011063771A JP5297491B2 (ja) | 2011-03-23 | 2011-03-23 | 半導体装置 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005231946A Division JP2007048958A (ja) | 2005-08-10 | 2005-08-10 | 半導体装置の製造方法および半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2011135102A true JP2011135102A (ja) | 2011-07-07 |
JP5297491B2 JP5297491B2 (ja) | 2013-09-25 |
Family
ID=44347418
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2011063771A Expired - Fee Related JP5297491B2 (ja) | 2011-03-23 | 2011-03-23 | 半導体装置 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5297491B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013197146A (ja) * | 2012-03-16 | 2013-09-30 | Renesas Electronics Corp | 半導体装置の製造方法及び半導体製造装置 |
JP2014007271A (ja) * | 2012-06-25 | 2014-01-16 | Disco Abrasive Syst Ltd | ウェーハの処理方法 |
CN111033687A (zh) * | 2017-08-31 | 2020-04-17 | 日本电气硝子株式会社 | 支承玻璃基板和使用其的层叠基板 |
WO2022190914A1 (ja) * | 2021-03-09 | 2022-09-15 | 東京エレクトロン株式会社 | 半導体チップの製造方法、及び基板処理装置 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003264205A (ja) * | 2002-03-08 | 2003-09-19 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2004022996A (ja) * | 2002-06-19 | 2004-01-22 | Mitsui Chemicals Inc | 半導体チップの積層方法 |
JP2005101312A (ja) * | 2003-09-25 | 2005-04-14 | Renesas Technology Corp | 半導体装置の製造方法 |
-
2011
- 2011-03-23 JP JP2011063771A patent/JP5297491B2/ja not_active Expired - Fee Related
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003264205A (ja) * | 2002-03-08 | 2003-09-19 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2004022996A (ja) * | 2002-06-19 | 2004-01-22 | Mitsui Chemicals Inc | 半導体チップの積層方法 |
JP2005101312A (ja) * | 2003-09-25 | 2005-04-14 | Renesas Technology Corp | 半導体装置の製造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013197146A (ja) * | 2012-03-16 | 2013-09-30 | Renesas Electronics Corp | 半導体装置の製造方法及び半導体製造装置 |
JP2014007271A (ja) * | 2012-06-25 | 2014-01-16 | Disco Abrasive Syst Ltd | ウェーハの処理方法 |
CN111033687A (zh) * | 2017-08-31 | 2020-04-17 | 日本电气硝子株式会社 | 支承玻璃基板和使用其的层叠基板 |
CN111033687B (zh) * | 2017-08-31 | 2023-10-24 | 日本电气硝子株式会社 | 支承玻璃基板和使用其的层叠基板 |
WO2022190914A1 (ja) * | 2021-03-09 | 2022-09-15 | 東京エレクトロン株式会社 | 半導体チップの製造方法、及び基板処理装置 |
Also Published As
Publication number | Publication date |
---|---|
JP5297491B2 (ja) | 2013-09-25 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2007048958A (ja) | 半導体装置の製造方法および半導体装置 | |
JP4796588B2 (ja) | 半導体装置の製造方法 | |
US9716080B1 (en) | Thin fan-out multi-chip stacked package structure and manufacturing method thereof | |
KR101182083B1 (ko) | 반도체 장치의 제조 방법 | |
JP2005340423A (ja) | 半導体装置の製造方法 | |
TWI733049B (zh) | 半導體封裝及其製造方法 | |
US20040097054A1 (en) | Fabrication method of semiconductor circuit device | |
JP5352624B2 (ja) | 半導体装置の製造方法 | |
TW200805569A (en) | Process for manufacturing semiconductor device | |
TW201128721A (en) | Manufacturing method of semiconductor device | |
JP2013080972A (ja) | 半導体装置の製造方法 | |
TWI381485B (zh) | Semiconductor device manufacturing method and semiconductor device | |
US20110230043A1 (en) | Tape residue-free bump area after wafer back grinding | |
JP5297491B2 (ja) | 半導体装置 | |
JP2014146829A (ja) | 半導体チップおよび半導体装置 | |
KR20070018713A (ko) | 반도체 장치의 제조 방법 및 반도체 장치 | |
US9269675B2 (en) | Semiconductor device and manufacturing method thereof | |
JP2011066294A (ja) | 半導体装置の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110323 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20130222 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20130226 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130424 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130521 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130614 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5297491 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
S531 | Written request for registration of change of domicile |
Free format text: JAPANESE INTERMEDIATE CODE: R313531 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
LAPS | Cancellation because of no payment of annual fees |