JP2005101312A - Manufacturing method of semiconductor device - Google Patents

Manufacturing method of semiconductor device Download PDF

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JP2005101312A
JP2005101312A JP2003333620A JP2003333620A JP2005101312A JP 2005101312 A JP2005101312 A JP 2005101312A JP 2003333620 A JP2003333620 A JP 2003333620A JP 2003333620 A JP2003333620 A JP 2003333620A JP 2005101312 A JP2005101312 A JP 2005101312A
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chip
adhesive
mounting substrate
semiconductor device
bonding
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JP2005101312A5 (en
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Tomoko Tono
朋子 東野
Kazunari Suzuki
一成 鈴木
Toshihiro Shiotsuki
敏弘 塩月
Hideyuki Suga
秀幸 須賀
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Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
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Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
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Priority to JP2003333620A priority Critical patent/JP2005101312A/en
Publication of JP2005101312A publication Critical patent/JP2005101312A/en
Publication of JP2005101312A5 publication Critical patent/JP2005101312A5/ja
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
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  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To surely bond a chip in the manufacturing process of a semiconductor device wherein a plurality of chips are laminated on a mounting substrate, without reducing the yield of the semiconductor device. <P>SOLUTION: A mask having a plane-shaped opening corresponding to the chip-mounting region on a mounting substrate 1 is disposed with the position of the opening registered with the chip-mounting region. A paste-like adhesive 4 is applied to the mounting substrate 1 on which the mask is disposed. After the opening of the mask is filled with the adhesive 4, the mask is removed to leave the adhesive 4 only in the chip-mounting region. Then, after the surface of the adhesive 4 is dried by heat treatment, the chip 6 is bonded to the adhesive 4 by thermocompression bonding. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、半導体装置の製造技術に関し、特に、複数の半導体チップを実装基板上に積層した構造を有する半導体装置の製造に適用して有効な技術に関するものである。   The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique that is effective when applied to the manufacture of a semiconductor device having a structure in which a plurality of semiconductor chips are stacked on a mounting substrate.

半導体装置の多機能化、高集積化および小型化を図ることを目的として、実装基板上に複数の半導体チップを三次元的に実装した積層パッケージが種々提案されている。   A variety of stacked packages in which a plurality of semiconductor chips are three-dimensionally mounted on a mounting substrate have been proposed for the purpose of achieving multi-functionality, high integration, and miniaturization of semiconductor devices.

また、メモリ製品等においては、同一の半導体チップを複数積層し、高集積化を図っているものもある。   Some memory products and the like have a plurality of identical semiconductor chips stacked to achieve high integration.

たとえば、特許文献１や２には、同一サイズの半導体ＩＣ素子を積層したチップ積層型パッケージ素子およびその製造方法についての記載がある。
特開２００３−７８１０６号公報 特開平６−２４４３６０号公報 For example, Patent Documents 1 and 2 describe a chip stack type package element in which semiconductor IC elements of the same size are stacked and a manufacturing method thereof.
JP 2003-78106 A JP-A-6-244360

本発明者らは、半導体装置の多機能化、高集積化、薄型化および小型化などを図ることを目的として、実装基板上に複数の半導体チップ（以下、単にチップと記す）を積層し、パッケージングする技術について検討している。その中で、下段のチップと実装基板との接着手段、および上段のチップと下段のチップとの接着手段については、以下の（ａ）〜（ｃ）のような例を検討した。
（ａ）下段のチップと実装基板とを熱硬化性樹脂接着材で接着し、上段のチップと下段のチップとを熱可塑性フィルム型接着材で接着する手段。
（ｂ）下段のチップと実装基板とを熱硬化性樹脂接着材で接着し、上段のチップと下段のチップとについても熱硬化性樹脂接着材で接着する手段。
（ｃ）下段のチップと実装基板とを熱可塑性フィルム型接着材で接着し、上段のチップと下段のチップとについても熱可塑性フィルム型接着材で接着する手段。 The present inventors have stacked a plurality of semiconductor chips (hereinafter simply referred to as chips) on a mounting substrate for the purpose of achieving multi-functionality, high integration, thinning, and miniaturization of a semiconductor device, We are studying packaging technology. Among them, the following examples (a) to (c) were examined for the bonding means between the lower chip and the mounting substrate and the bonding means between the upper chip and the lower chip.
(A) Means for bonding the lower chip and the mounting substrate with a thermosetting resin adhesive, and bonding the upper chip and the lower chip with a thermoplastic film type adhesive.
(B) Means in which the lower chip and the mounting substrate are bonded with a thermosetting resin adhesive, and the upper chip and the lower chip are also bonded with the thermosetting resin adhesive.
(C) Means for bonding the lower chip and the mounting substrate with a thermoplastic film adhesive, and bonding the upper chip and the lower chip with the thermoplastic film adhesive.

また、半導体装置の薄型化および小型化を図るために、チップの厚さについては、たとえば１５０μｍ〜３００μｍ程度だったものを２０〜１００μｍ程度にまで薄くすることが要求され、チップと実装基板との接着および２つのチップ間の接着に用いる接着材についても、チップの厚さより薄い、たとえば１０μｍ〜３０μｍとすることが求められている。このような薄型化されたチップを上記（ａ）、（ｂ）または（ｃ）の接着手段を用いて実装基板上に積層する場合には、以下のような課題が存在することを本発明者らは見出した。   Further, in order to reduce the thickness and size of the semiconductor device, it is required to reduce the thickness of the chip from about 150 μm to 300 μm to about 20 to 100 μm. The adhesive used for bonding and bonding between two chips is also required to be thinner than the chip thickness, for example, 10 μm to 30 μm. In the case where such a thinned chip is laminated on a mounting substrate using the bonding means (a), (b) or (c), the present inventors have the following problems. Found.

すなわち、上記（ａ）または（ｂ）の接着手段を用いた場合には、薄いチップの側面から接着材が這い上がり、その接着材がチップの上面に付着することによってチップの耐湿信頼性が低下してしまう課題が存在する。その這い上がった接着材がチップ上面のボンディングパッドに付着した場合には、ワイヤとそのボンディングパッドとの接合不良が発生してしまう課題が存在する。また、パッケージの小型化に伴って、チップと実装基板上に形成されたボンディングパッドとの距離マージンが確保し難くなっており、接着材が実装基板上に広がり、その実装基板上に形成されたボンディングパッドに付着してしまうことが懸念される。接着材が実装基板上に形成されたボンディングパッドに付着してしまった場合においても、ワイヤの接合不良が発生してしまう課題が存在する。これらの課題は、チップの薄型化およびパッケージの小型化が進むに従って解決し難くなる。   That is, when the adhesive means (a) or (b) is used, the adhesive crawls up from the side surface of the thin chip, and the adhesive adheres to the upper surface of the chip, thereby reducing the moisture resistance reliability of the chip. There is a problem to do. When the scooped adhesive material adheres to the bonding pad on the upper surface of the chip, there is a problem that a bonding failure between the wire and the bonding pad occurs. In addition, with the miniaturization of the package, it has become difficult to secure a distance margin between the chip and the bonding pad formed on the mounting substrate, and the adhesive spreads on the mounting substrate and is formed on the mounting substrate. There is a concern that it may adhere to the bonding pad. Even when the adhesive material adheres to the bonding pad formed on the mounting substrate, there is a problem that a bonding failure of the wire occurs. These problems become difficult to solve as the chip becomes thinner and the package becomes smaller.

また、チップの厚さが薄くなるに従って、チップの主面（素子形成面）に形成された部材とその下部の部材との熱膨張率の差等に起因する応力の差が生じ、チップの反りが大きくなる。この反りは、たとえば７ｍｍ〜８ｍｍ角のチップで２０μｍ程度になる。このようなチップを熱硬化性樹脂接着材で接着しようとしても、その熱硬化性樹脂接着材が硬化する時にはチップが反ったままの状態となる。チップが反ったままの状態で接着材が硬化してしまうと、チップの接着面の全面で均一な接着材の濡れ性を確保できなくなり、接着不良を引き起こしてしまう課題が存在する。また、チップの接着面の全面で均一な接着材の濡れ性が確保できない場合には、チップの接着面に気泡を含んで接着材が硬化してしまう虞があり、この気泡がリフロー工程時に膨張してチップが割れてしまう課題も存在する。   Further, as the thickness of the chip becomes thinner, a difference in stress caused by a difference in thermal expansion coefficient between a member formed on the main surface (element formation surface) of the chip and a member below the chip occurs, and the warpage of the chip occurs. Becomes larger. For example, this warpage is about 20 μm with a 7 mm to 8 mm square chip. Even if such a chip is to be bonded with a thermosetting resin adhesive, the chip remains warped when the thermosetting resin adhesive is cured. If the adhesive is cured while the chip is warped, there is a problem in that uniform wettability of the adhesive cannot be ensured over the entire bonding surface of the chip, resulting in poor adhesion. In addition, if uniform wettability of the adhesive cannot be ensured over the entire adhesive surface of the chip, there is a risk that the adhesive will harden by including bubbles on the adhesive surface of the chip, and these bubbles expand during the reflow process. There is also a problem that the chip breaks.

一方、上記（ｃ）の接着手段を用いた場合には、実装基板の表面に形成された配線パターンに起因する凹凸（１０μｍ〜３０μｍ程度）を厚さ１０μｍ〜３０μｍ程度の熱可塑性フィルム型接着材では埋め込むことができない。そのため、接着面全面で均一な濡れ性を確保できなくなり、その凹凸部にて接着不良を生じてしまう課題が存在する。このような接着不良は、後のリフロー工程時にチップの割れや剥離を引き起こす原因となる。   On the other hand, when the adhesive means (c) is used, a thermoplastic film type adhesive having unevenness (about 10 μm to 30 μm) due to the wiring pattern formed on the surface of the mounting substrate having a thickness of about 10 μm to 30 μm. Can not be embedded. For this reason, there is a problem that uniform wettability cannot be ensured over the entire bonding surface, and adhesion failure occurs in the uneven portion. Such poor adhesion causes cracking and peeling of the chip during the subsequent reflow process.

本発明の目的は、実装基板上に複数のチップが積層された半導体装置の製造工程において、半導体装置の歩留りを低下させることなくチップを確実に接着できる技術を提供することにある。   An object of the present invention is to provide a technique capable of reliably bonding chips without reducing the yield of the semiconductor device in a manufacturing process of a semiconductor device in which a plurality of chips are stacked on a mounting substrate.

本発明の前記ならびにその他の目的と新規な特徴は、本明細書の記述および添付図面から明らかになるであろう。   The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

本願において開示される発明のうち、代表的なものの概要を簡単に説明すれば、次のとおりである。   Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

すなわち、本発明による半導体装置の製造方法は、
（ａ）実装基板の主面に選択的に樹脂接着材を塗布する工程と、
（ｂ）前記実装基板に熱処理を施し、前記樹脂接着材を半硬化させる工程と、
（ｃ）前記（ｂ）工程後、前記樹脂接着材を介して第１半導体チップを前記樹脂接着材を塗布した領域に接着する工程とを含む。 That is, a method for manufacturing a semiconductor device according to the present invention includes:
(A) a step of selectively applying a resin adhesive to the main surface of the mounting substrate;
(B) applying heat treatment to the mounting substrate and semi-curing the resin adhesive;
(C) After the step (b), including a step of adhering the first semiconductor chip to the region where the resin adhesive is applied via the resin adhesive.

本願において開示される発明のうち、代表的なものによって得られる効果を簡単に説明すれば以下のとおりである。
（１）半導体装置の歩留りを低下させることなく、確実にチップを実装基板に接着することができる。
（２）実装基板上に複数のチップが積層された半導体装置の製造工程工程数を低減することができる。 Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.
(1) The chip can be securely bonded to the mounting substrate without reducing the yield of the semiconductor device.
(2) The number of manufacturing process steps for a semiconductor device in which a plurality of chips are stacked on a mounting substrate can be reduced.

以下、本発明の実施の形態を図面に基づいて詳細に説明する。なお、実施の形態を説明するための全図において、同一の部材には原則として同一の符号を付し、その繰り返しの説明は省略する。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

（実施の形態１）
本実施の形態１の半導体装置およびその製造工程について、図１〜図１１を用いて工程に沿って説明する。 (Embodiment 1)
The semiconductor device according to the first embodiment and the manufacturing process thereof will be described along the process with reference to FIGS.

まず、図１に示すように、チップ搭載用の実装基板１を用意する。この実装基板１は、たとえばエポキシ樹脂（ガラス・エポキシ樹脂）のような汎用樹脂を主体として形成された多層配線基板である。すなわち、表面や裏面に配線を印刷法で形成した、いわゆるプリント基板を複数積層した構造となっており、この複数層のプリント基板の各配線は、各プリント基板に形成されたビアホールを通じて電気的に接続されている。また、実装基板１の主面（チップ搭載面）には、複数のボンディングワイヤ接続用のパッドＰＤ１が形成されている。このパッドＰＤ１は、たとえば実装基板１の外周部に沿って配置される。   First, as shown in FIG. 1, a mounting substrate 1 for chip mounting is prepared. The mounting board 1 is a multilayer wiring board formed mainly of a general-purpose resin such as an epoxy resin (glass / epoxy resin). That is, it has a structure in which a plurality of so-called printed circuit boards are formed by forming wiring on the front and back surfaces by a printing method, and each wiring of this multi-layer printed circuit board is electrically connected through a via hole formed in each printed circuit board. It is connected. In addition, a plurality of bonding wire connection pads PD1 are formed on the main surface (chip mounting surface) of the mounting substrate 1. The pad PD1 is disposed along the outer peripheral portion of the mounting substrate 1, for example.

続いて、その実装基板１上に、接着材塗布領域に対応した平面形状の開口部２を有するマスク３を、その開口部２の位置を接着材塗布領域に合わせて配置する。この時、パッドＰＤ１は、マスク３によって覆われる。本実施の形態１において、マスク３としては、後の工程で実装基板１上に接着（搭載）するチップの厚さより薄い厚さのものを用いるものであり、厚さ３０μｍ程度以下のシルクスクリーンまたはメタルマスクなどを用いることを例示できる。続いて、常温（室温）で、マスク３が配置された実装基板１上に接着材４を塗布する。この接着材４は、ペースト状であり、たとえば熱可塑性の樹脂接着材、一部が熱可塑性を有し一部が熱硬化性を有する半熱可塑半熱硬化性の樹脂接着材、または熱硬化性の樹脂接着材などを用いることができる。   Subsequently, a mask 3 having a planar opening 2 corresponding to the adhesive application region is disposed on the mounting substrate 1 so that the position of the opening 2 is aligned with the adhesive application region. At this time, the pad PD1 is covered with the mask 3. In the first embodiment, as the mask 3, a mask having a thickness smaller than the thickness of a chip to be bonded (mounted) on the mounting substrate 1 in a later process is used. The use of a metal mask or the like can be exemplified. Subsequently, the adhesive 4 is applied on the mounting substrate 1 on which the mask 3 is disposed at room temperature (room temperature). This adhesive 4 is in the form of a paste, for example, a thermoplastic resin adhesive, a semi-thermoplastic semi-thermosetting resin adhesive that is partly thermoplastic and partly thermosetting, or thermosetting. May be used.

次に、図１および図２に示すように、スキージ５を用いて開口部２内に接着材４を埋め込む。続いて、図３に示すように、実装基板１上からマスク３を取り外す。これにより、実装基板１上においては、接着材塗布領域にのみ厚さ３０μｍ程度以下の接着材４を残すことができる。   Next, as shown in FIGS. 1 and 2, the adhesive 4 is embedded in the opening 2 using a squeegee 5. Subsequently, as shown in FIG. 3, the mask 3 is removed from the mounting substrate 1. Thereby, on the mounting substrate 1, the adhesive 4 having a thickness of about 30 μm or less can be left only in the adhesive application region.

次に、図４に示すように、たとえば実装基板１に８０℃〜２００℃程度の熱処理を施すことによって、接着材４を硬化中間状態である、半硬化状態にする。   Next, as shown in FIG. 4, for example, the mounting substrate 1 is subjected to a heat treatment of about 80 ° C. to 200 ° C. to bring the adhesive 4 into a semi-cured state, which is a cured intermediate state.

次に、図５に示すように、常温（室温）〜２００℃程度の雰囲気中にて、チップ（第１半導体チップ）６を接着材４に圧着する。この時、チップ６に加える圧力は１００ｇ〜１ｋｇ程度とし、圧着時間は１秒程度とすることを例示できる。本実施の形態１においては、チップ６として、厚さが２０μｍ〜１００μｍ程度のものを例示する。また、チップ６中には複数の半導体素子および配線が形成され、その表面は保護膜で覆われている。また、その保護膜に設けられた複数の開口部からは、それぞれボンディングワイヤ接続用のパッドＰＤ２が露出している。パッドＰＤ２は、チップ６内に形成された最上層配線の一部であり、たとえばチップ６の外周部に沿って配置されている。   Next, as shown in FIG. 5, the chip (first semiconductor chip) 6 is pressure-bonded to the adhesive 4 in an atmosphere of room temperature (room temperature) to about 200 ° C. At this time, the pressure applied to the chip 6 is about 100 g to 1 kg, and the pressing time is about 1 second. In the first embodiment, the chip 6 having a thickness of about 20 μm to 100 μm is exemplified. Further, a plurality of semiconductor elements and wirings are formed in the chip 6 and the surface thereof is covered with a protective film. Further, pads PD2 for bonding wire connection are exposed from a plurality of openings provided in the protective film. The pad PD2 is a part of the uppermost layer wiring formed in the chip 6, and is disposed along the outer peripheral portion of the chip 6, for example.

次に、図６に示すように、チップ６の搭載された実装基板１に８０℃〜２００℃程度の熱処理を施す。それにより、接着材４を硬化させて、チップ６の実装基板１への接着を強固にすることができる。   Next, as shown in FIG. 6, a heat treatment at about 80 ° C. to 200 ° C. is performed on the mounting substrate 1 on which the chip 6 is mounted. Thereby, the adhesive 4 can be hardened and the adhesion of the chip 6 to the mounting substrate 1 can be strengthened.

上記の工程でチップ６を実装基板１へ接着する本実施の形態１によれば、チップ６の厚さが２０μｍ〜１００μｍ程度と薄い場合でも、チップ６を実装基板１へ搭載する時には、接着材４は厚さがチップ６より薄く、かつ半硬化した状態となっているので、接着材４がチップ６の側面から這い上がり、チップ６の上面に付着してしまうことを防ぐことができる。それにより、チップ６の耐湿信頼性が低下してしまうことを防ぐことが可能となる。接着材４がチップ６の側面から這い上がり、パッドＰＤ２に付着した場合には、後のワイヤボンディング工程でワイヤとパッドＰＤ２との接合不良が発生してしまうことが懸念されるが、本実施の形態１によればそのような不具合も防ぐことができる。   According to the first embodiment in which the chip 6 is bonded to the mounting substrate 1 in the above process, even when the thickness of the chip 6 is as thin as about 20 μm to 100 μm, when the chip 6 is mounted on the mounting substrate 1, the adhesive Since the thickness 4 is thinner than the chip 6 and is semi-cured, it is possible to prevent the adhesive 4 from creeping up from the side surface of the chip 6 and adhering to the upper surface of the chip 6. As a result, it is possible to prevent the moisture resistance reliability of the chip 6 from being lowered. If the adhesive 4 crawls up from the side surface of the chip 6 and adheres to the pad PD2, there is a concern that a bonding failure between the wire and the pad PD2 may occur in a later wire bonding step. According to the first aspect, such a problem can also be prevented.

また、パッケージの小型化に伴って、チップ６と実装基板１上に形成されたパッドＰＤ１との間の距離が小さくなっている場合には、粘性の低いペースト状の接着材を用いてチップ６と実装基板１とを接着すると、接着材が実装基板１上に広がり、パッドＰＤ１に付着してしまう不具合が懸念される。一方、上記の本実施の形態１のように、チップ６の接着時において、接着材４をチップ６より薄くし、かつ印刷による塗布時に比べて粘性の高い半硬化状態としておくことによって、そのような不具合を防ぐことができる。それにより、後のワイヤボンディング工程でワイヤとパッドＰＤ１との接合不良が発生してしまうことを防ぐことが可能になる。   Further, when the distance between the chip 6 and the pad PD1 formed on the mounting substrate 1 is reduced with the miniaturization of the package, the chip 6 is made using a paste-like adhesive material having low viscosity. When the mounting substrate 1 is bonded to the mounting substrate 1, there is a concern that the adhesive spreads on the mounting substrate 1 and adheres to the pad PD1. On the other hand, as in the first embodiment, when the chip 6 is bonded, the adhesive 4 is made thinner than the chip 6 and is in a semi-cured state having a higher viscosity than that of application by printing. Can be prevented. As a result, it is possible to prevent a bonding failure between the wire and the pad PD1 from occurring in a later wire bonding step.

また、チップ６の厚さが薄くなるに従って、チップ６の主面（素子形成面）に形成された部材とその下部の部材との熱膨張率の差等に起因する応力の差が生じ、チップ６の反りが大きくなる。このように反ってしまったチップ６を、たとえば熱硬化性樹脂接着材で接着しようとすると、チップ６が反ったままの状態で熱硬化性樹脂接着材が硬化してしまい、チップ６の接着面の全面で均一な接着材の濡れ性を確保できなくなり、接着不良を引き起こしてしまう不具合が懸念される。チップ６の接着面の全面で均一な接着材の濡れ性が確保できない場合には、チップ６の接着面に気泡を含んで接着材が硬化してしまう虞があり、この気泡が後のリフロー工程時に膨張してチップ６が割れてしまう不具合も懸念される。一方、上記の本実施の形態１の接着手段では、チップ６が反っている場合でも、熱圧着することによって、接着後においてチップ６を平坦な状態で固定できる。それにより、チップ６の接着面の全面で均一な接着材の濡れ性を確保し、チップ６を平坦な状態で実装基板１に接着することができる。それにより、前述したチップ６の接着不良および割れといった不具合を防ぐことができる。   Further, as the thickness of the chip 6 becomes thinner, a difference in stress is generated due to a difference in thermal expansion coefficient between a member formed on the main surface (element forming surface) of the chip 6 and a member below the chip 6. 6 warp increases. If the chip 6 that has been warped in this way is to be bonded with, for example, a thermosetting resin adhesive, the thermosetting resin adhesive is cured while the chip 6 is warped, and the bonding surface of the chip 6 is fixed. There is a concern that the wettability of the uniform adhesive material cannot be ensured over the entire surface of the film, and a defect that causes poor adhesion occurs. If uniform wettability of the adhesive cannot be ensured over the entire adhesive surface of the chip 6, there is a possibility that the adhesive will contain air bubbles on the adhesive surface of the chip 6, and the air bubbles may be cured later. There is a concern that the chip 6 sometimes expands and the chip 6 breaks. On the other hand, in the bonding means of the first embodiment, even when the chip 6 is warped, the chip 6 can be fixed in a flat state after bonding by thermocompression bonding. Thereby, uniform wettability of the adhesive can be ensured over the entire bonding surface of the chip 6, and the chip 6 can be bonded to the mounting substrate 1 in a flat state. As a result, it is possible to prevent problems such as adhesion failure and cracking of the chip 6 described above.

また、本実施の形態１の接着材４のような樹脂接着材の代わりにフィルム状接着材を用いてチップ６を実装基板１に接着する場合には、実装基板１の表面に形成された配線パターンに起因する凹凸をフィルム状接着材では埋め込むことができず、接着面全面で均一な濡れ性を確保できなくなり、その凹凸部にて接着不良を生じてしまうことが懸念される。このような接着不良が生じた場合には、後のリフロー工程時にチップ６の割れや剥離といった不具合の発生が懸念される。一方、上記の本実施の形態１の接着手段では、接着材４として粘性の低いペースト状の接着材を用いるので、実装基板１の表面に形成された配線パターンに起因する凹凸を接着材４で埋め込むことができる。それにより、チップ６の接着面の全面で均一な接着材の濡れ性を確保できるので、前述したチップ６の割れや剥離といった不具合を防ぐことが可能となる。   When the chip 6 is bonded to the mounting substrate 1 using a film adhesive instead of the resin adhesive such as the adhesive 4 of the first embodiment, the wiring formed on the surface of the mounting substrate 1 It is feared that unevenness due to the pattern cannot be embedded with the film adhesive, and uniform wettability cannot be secured over the entire bonding surface, resulting in poor adhesion at the uneven portion. When such an adhesion failure occurs, there is a concern that a defect such as cracking or peeling of the chip 6 may occur during the subsequent reflow process. On the other hand, since the adhesive means of the first embodiment uses a paste-like adhesive having a low viscosity as the adhesive 4, unevenness caused by the wiring pattern formed on the surface of the mounting substrate 1 is eliminated by the adhesive 4. Can be embedded. As a result, uniform wettability of the adhesive can be ensured over the entire bonding surface of the chip 6, so that the above-described problems such as cracking and peeling of the chip 6 can be prevented.

ところで、図４を用いて説明した熱処理後において、ペースト状の状態に比較して、粘性の高い半硬化状態となった接着材４が、チップ６を接着しかつ搬送時にチップ６が剥離しない程度以上のタック性（接着性）を有している場合には、そのタック性を利用してチップ６を仮接着状態にして、図５を用いて説明した熱圧着工程および図６を用いて説明した熱処理工程を省略してその後の工程を進めてもよい。すなわち、チップ６上にさらに他のチップを積層する際の熱圧着工程および熱処理工程で一括して処理することもできる。   By the way, after the heat treatment described with reference to FIG. 4, the adhesive 4 in a semi-cured state having a higher viscosity than the pasty state adheres the chip 6 and does not peel off the chip 6 during transportation. In the case of having the above tack property (adhesiveness), the chip 6 is temporarily bonded using the tack property, and the thermocompression bonding process described with reference to FIG. 5 and the description with reference to FIG. The subsequent heat treatment step may be omitted and the subsequent steps may proceed. That is, it is possible to perform batch processing in a thermocompression bonding process and a heat treatment process when another chip is stacked on the chip 6.

次に、図７に示すように、裏面にフィルム状の接着材７が貼付されたチップ（第２半導体チップ）８を用意する。チップ８の裏面へ接着材７を貼り付けるには、たとえば半導体ウエハを個々のチップ８へ分割する前に、その半導体ウエハの裏面を研削して所定の厚さにした後、半導体ウエハの裏面全面に熱可塑性のフィルム状の接着材７を貼付し、その後、接着材７ごと半導体ウエハを個々のチップ８へ分割することで実現できる。本実施の形態１においては、チップ８として、厚さが２０μｍ〜１００μｍ程度のものを例示する。また、チップ８中には複数の半導体素子および配線が形成され、その表面は保護膜で覆われている。その保護膜に設けられた複数の開口部からは、それぞれボンディングワイヤ接続用のパッドＰＤ３が露出している。パッドＰＤ３は、チップ８内に形成された最上層配線の一部であり、たとえばチップ８の外周部に沿って配置されている。   Next, as shown in FIG. 7, a chip (second semiconductor chip) 8 having a film-like adhesive 7 attached to the back surface is prepared. In order to attach the adhesive 7 to the back surface of the chip 8, for example, before dividing the semiconductor wafer into individual chips 8, the back surface of the semiconductor wafer is ground to a predetermined thickness, and then the entire back surface of the semiconductor wafer. It can be realized by attaching a thermoplastic film adhesive 7 to the substrate and then dividing the semiconductor wafer together with the adhesive 7 into individual chips 8. In the first embodiment, the chip 8 is exemplified as having a thickness of about 20 μm to 100 μm. Further, a plurality of semiconductor elements and wirings are formed in the chip 8, and the surface thereof is covered with a protective film. From the plurality of openings provided in the protective film, bonding wire connection pads PD3 are respectively exposed. The pad PD3 is a part of the uppermost layer wiring formed in the chip 8, and is disposed along the outer peripheral portion of the chip 8, for example.

続いて、チップ６が接着された実装基板１を加熱ステージＨＳ上に配置し、１００℃〜２００℃程度の温度で加熱する。その状態で、チップ６上に上記接着材７を介してチップ８を熱圧着する。この時、チップ８に加える圧力は１００ｇ〜５００ｇ程度とし、熱圧着時間は１秒程度とすることを例示できる。チップ８の接着に熱可塑性のフィルム状の接着材７を用いることにより、接着材７がチップ８の側面から這い上がり、チップ８の上面に付着してしまうことを防ぐことができる。それにより、チップ８の耐湿信頼性が低下してしまうことを防ぐことが可能となる。接着材７がチップ８の側面から這い上がり、パッドＰＤ３に付着した場合には、後のワイヤボンディング工程でワイヤとパッドＰＤ３との接合不良が発生してしまうことが懸念されるが、本実施の形態１によればそのような不具合も防ぐことができる。また、パッケージの小型化に伴って、チップ８とチップ６に形成されたパッドＰＤ２との間の距離が小さくなっている場合においても、接着材７がチップ６上に広がってパッドＰＤ２に付着してしまうような不具合を防ぐことができる。それにより、後のワイヤボンディング工程でワイヤとパッドＰＤ２との接合不良が発生してしまうことを防ぐことが可能になる。   Subsequently, the mounting substrate 1 to which the chip 6 is bonded is placed on the heating stage HS and heated at a temperature of about 100 ° C. to 200 ° C. In this state, the chip 8 is thermocompression bonded onto the chip 6 via the adhesive material 7. At this time, the pressure applied to the chip 8 is about 100 to 500 g, and the thermocompression bonding time is about 1 second. By using the thermoplastic film adhesive 7 for bonding the chip 8, it is possible to prevent the adhesive 7 from scooping up from the side surface of the chip 8 and adhering to the upper surface of the chip 8. Thereby, it becomes possible to prevent the moisture resistance reliability of the chip 8 from being lowered. When the adhesive 7 crawls up from the side surface of the chip 8 and adheres to the pad PD3, there is a concern that a bonding failure between the wire and the pad PD3 may occur in a later wire bonding step. According to the first aspect, such a problem can also be prevented. Further, even when the distance between the chip 8 and the pad PD2 formed on the chip 6 is reduced with the miniaturization of the package, the adhesive 7 spreads on the chip 6 and adheres to the pad PD2. It is possible to prevent malfunctions that would occur. As a result, it is possible to prevent a bonding failure between the wire and the pad PD2 from occurring in a later wire bonding step.

また、前述したチップ６の場合と同様に、チップ８が接着時に反っている場合でも、チップ６への接着は熱圧着により行われるので、接着後においてチップ８を平坦な状態で固定できる。   Similarly to the case of the chip 6 described above, even when the chip 8 is warped during bonding, the chip 6 can be fixed in a flat state after bonding because the bonding to the chip 6 is performed by thermocompression bonding.

続いて、チップ６、８の搭載された実装基板１に８０℃〜２００℃程度の熱処理を施す。それにより、接着材７を硬化させて、チップ８のチップ６への接着を強固にすることができる。   Subsequently, a heat treatment at about 80 ° C. to 200 ° C. is performed on the mounting substrate 1 on which the chips 6 and 8 are mounted. Thereby, the adhesive 7 can be hardened and the adhesion of the chip 8 to the chip 6 can be strengthened.

ところで、図４を用いて説明した熱処理後において、半硬化状態となった接着材４が、チップ６を接着しかつ搬送時にチップ６が剥離しない程度以上のタック性（接着性）を有している場合には、そのタック性を利用してチップ６を仮接着状態にして、図５を用いて説明した熱圧着工程および図６を用いて説明した熱処理工程を省略してもよい旨を前述したが、その熱圧着工程をチップ８のチップ６への熱圧着工程で一括して行い、その熱処理工程をチップ８の搭載後の熱処理工程で一括して行ってもよい。それにより、本実施の形態の半導体装置の製造工程数を低減することができる。   By the way, after the heat treatment described with reference to FIG. 4, the adhesive 4 that has become a semi-cured state has a tack property (adhesiveness) that is higher than the level that the chip 6 adheres and the chip 6 does not peel off during transportation. If it is, the chip 6 may be temporarily bonded using the tackiness, and the heat pressing step described with reference to FIG. 5 and the heat treatment step described with reference to FIG. 6 may be omitted. However, the thermocompression bonding process may be performed collectively in the thermocompression bonding process of the chip 8 to the chip 6, and the heat treatment process may be performed in the heat treatment process after mounting the chip 8. Thereby, the number of manufacturing steps of the semiconductor device of this embodiment can be reduced.

また、接着材４が、半硬化状態のままでもチップ６を搭載する場合、およびその後の工程において問題を起こす可能性が十分に小さい場合には、チップ６搭載時の加熱、あるいはその後に接着材４に施す熱処理工程が不要になる場合もある。   Further, when the chip 6 is mounted even when the adhesive 4 remains in a semi-cured state, and when the possibility of causing a problem in the subsequent process is sufficiently small, heating when the chip 6 is mounted, or after that, 4 may be unnecessary.

また、ペースト状の接着材を塗布した工程の後に、熱処理などの工程によって接着材が常温で完全に硬化する状態にしてもよい。また、その場合には、その後のチップを搭載する工程において、接着材の熱可塑性を利用して、接着材を加熱することによって、接着材が適当な粘性を保つ程度に軟化させた状態でチップ６を搭載してもよい。   Further, after the step of applying the paste adhesive, the adhesive may be completely cured at room temperature by a process such as heat treatment. In that case, in the subsequent chip mounting process, the chip is softened to such an extent that the adhesive is kept at an appropriate viscosity by heating the adhesive using the thermoplasticity of the adhesive. 6 may be mounted.

また、ペースト状の接着材を塗布する工程の後に、接着材を半硬化する方法としては、熱を加える方法に限らない。たとえば、接着材が紫外線に反応して硬化する性質を持つ場合には、紫外線を照射することによって半硬化あるいは硬化させてもよい。   Further, the method of semi-curing the adhesive after the step of applying the paste adhesive is not limited to the method of applying heat. For example, when the adhesive has a property of curing in response to ultraviolet rays, it may be semi-cured or cured by irradiating with ultraviolet rays.

次に、図８に示すように、実装基板１を加熱ステージＨＳ上に搭載し、約１００℃〜２５０℃で加熱しながら、実装基板１上のパッドＰＤ１とチップ６のパッドＰＤ２とをワイヤ９で電気的に接続（ワイヤボンディング）し、実装基板１上のパッドＰＤ１とチップ８のパッドＰＤ３とをワイヤ１０で電気的に接続する。本実施の形態１において、ワイヤ９、１０は、Ａｕ（金）などの導電性材料とすることを例示でき、ワイヤボンディング処理は、超音波振動と熱圧着とを併用したワイヤボンダを使用して行うことを例示できる。   Next, as shown in FIG. 8, the mounting substrate 1 is mounted on the heating stage HS, and the pad PD1 on the mounting substrate 1 and the pad PD2 of the chip 6 are connected to the wire 9 while heating at about 100 ° C. to 250 ° C. Are electrically connected (wire bonding), and the pad PD1 on the mounting substrate 1 and the pad PD3 of the chip 8 are electrically connected by the wire 10. In the first embodiment, the wires 9 and 10 can be exemplified as conductive materials such as Au (gold), and the wire bonding process is performed using a wire bonder that uses both ultrasonic vibration and thermocompression bonding. This can be illustrated.

次に、図９に示すように、実装基板１、チップ６、８、およびワイヤ９、１０を金型（図示は省略）で挟持し、その金型のキャビティ内に１５０℃〜２００℃程度で溶融したモールド樹脂１１を注入し、実装基板１、チップ６、８、およびワイヤ９、１０をそのモールド樹脂１１によって封止する。金型のキャビティ内へのモールド樹脂１１の注入時には、金型もモールド樹脂１１と同程度の温度で加熱しておく。また、図６を用いて説明した熱処理工程および図７を用いて説明した熱処理工程における温度条件が、このモールド樹脂１１による封止工程時の温度と合致する場合には、前述の熱処理をこの封止工程時の熱を利用して一括して行ってもよい。   Next, as shown in FIG. 9, the mounting substrate 1, the chips 6 and 8, and the wires 9 and 10 are sandwiched between molds (not shown), and the mold cavity has a temperature of about 150 ° C. to 200 ° C. Molten mold resin 11 is injected, and mounting substrate 1, chips 6 and 8, and wires 9 and 10 are sealed with mold resin 11. When the mold resin 11 is injected into the mold cavity, the mold is also heated at the same temperature as the mold resin 11. Further, if the temperature conditions in the heat treatment step described with reference to FIG. 6 and the heat treatment step described with reference to FIG. You may carry out collectively using the heat | fever at the time of a stop process.

次に、図１０に示すように、実装基板１側を上面とし、実装基板１上にバンプ電極１２を形成する。このバンプ電極１２は、たとえばＳｎ（スズ）−Ａｇ（銀）−Ｃｕ（銅）共晶合金から形成されたはんだボールを実装基板１の上面（チップ搭載側の逆側）に供給した後、実装基板１等を２４０℃〜２６０℃の雰囲気中に配置し、はんだボールをリフローすることで形成することができる。その後、図１１に示すように、バンプ電極１２の形成面を下側とし、本実施の形態１の半導体装置が略完成する。   Next, as shown in FIG. 10, the bump electrode 12 is formed on the mounting substrate 1 with the mounting substrate 1 side as an upper surface. The bump electrode 12 is mounted after supplying a solder ball formed of, for example, a Sn (tin) -Ag (silver) -Cu (copper) eutectic alloy to the upper surface (the opposite side of the chip mounting side) of the mounting substrate 1. It can be formed by placing the substrate 1 or the like in an atmosphere of 240 ° C. to 260 ° C. and reflowing the solder balls. Thereafter, as shown in FIG. 11, the semiconductor device of the first embodiment is substantially completed with the formation surface of the bump electrode 12 on the lower side.

ところで、上記の本実施の形態１では、チップを２段に積層する例について説明したが、さらに多段に積層してもよい。たとえば、図１２に示すように、チップ８をチップ６に積層した手段と同様の手段により、チップ１４をチップ８に積層する。すなわち、接着材７と同様の熱可塑性のフィルム状の接着材１５を用いてチップ１４をチップ８に熱圧着し、ワイヤ９、１０と同様のワイヤ１６によって、チップ１４に形成されたパッドＰＤ４と実装基板１上のパッドＰＤ１とを電気的に接続するものである。   By the way, in the above-described first embodiment, the example in which the chips are stacked in two stages has been described. However, the chips may be stacked in more stages. For example, as shown in FIG. 12, the chip 14 is stacked on the chip 8 by means similar to the means for stacking the chip 8 on the chip 6. That is, the chip 14 is thermocompression-bonded to the chip 8 using the thermoplastic film-like adhesive 15 similar to the adhesive 7, and the pad PD 4 formed on the chip 14 with the wire 16 similar to the wires 9 and 10. The pad PD1 on the mounting substrate 1 is electrically connected.

（実施の形態２）
本実施の形態２の半導体装置は、たとえば平面で実装基板上に複数のチップが配置されたＭＣＭ（Multi Chip Module）である。このような本実施の形態２の半導体装置およびその製造工程について、図１３〜図１６を用いて工程に沿って説明する。 (Embodiment 2)
The semiconductor device according to the second embodiment is, for example, an MCM (Multi Chip Module) in which a plurality of chips are arranged on a mounting substrate in a plane. Such a semiconductor device according to the second embodiment and a manufacturing process thereof will be described along the process with reference to FIGS.

まず、図１３に示すように、前記実施の形態１で用いた実装基板１と同様のチップ搭載用の実装基板１Ａを用意する。実装基板１Ａの接着材塗布領域には、たとえば２箇所のチップ搭載領域が設けられ、その接着材塗布領域の周りには複数のボンディングワイヤ接続用のパッドＰＤ１Ａ、ＰＤ１Ｂが形成されている。   First, as shown in FIG. 13, a mounting substrate 1A for chip mounting similar to the mounting substrate 1 used in the first embodiment is prepared. For example, two chip mounting regions are provided in the adhesive material application region of the mounting substrate 1A, and a plurality of bonding wire connection pads PD1A and PD1B are formed around the adhesive material application region.

続いて、その実装基板１Ａ上に、前記実施の形態１におけるマスク３（図１参照）と同様に、実装基板１Ａ上の接着材塗布領域に対応した平面形状の開口部２Ａ、２Ｂを有するマスク３Ａを、その開口部２Ａ、２Ｂの位置を接着材塗布領域に合わせて配置する。この時、パッドＰＤ１Ａ、ＰＤ１Ｂは、マスク３Ａによって覆われる。次いで、前記実施の形態１にて図１および図２を用いて説明した工程と同様の工程によって、実装基板１Ａ上に接着材４を塗布し、スキージ５を用いて開口部２Ａ、２Ｂ内に接着材４を埋め込む（図１４参照）。次いで、図１５に示すように、実装基板１Ａ上からマスク３Ａを取り外す。これにより、実装基板１Ａ上においては、接着材塗布領域にのみ選択的に接着材４を残すことができる。   Subsequently, similarly to the mask 3 (see FIG. 1) in the first embodiment, a mask having planar openings 2A and 2B corresponding to the adhesive application region on the mounting substrate 1A on the mounting substrate 1A. 3A is arranged so that the positions of the openings 2A and 2B are aligned with the adhesive application region. At this time, the pads PD1A and PD1B are covered with the mask 3A. Next, the adhesive 4 is applied on the mounting substrate 1A by the same process as that described in the first embodiment with reference to FIGS. 1 and 2, and the squeegee 5 is used to open the openings 2A and 2B. The adhesive 4 is embedded (see FIG. 14). Next, as shown in FIG. 15, the mask 3A is removed from the mounting substrate 1A. Thereby, on the mounting substrate 1A, the adhesive 4 can be selectively left only in the adhesive application region.

その後、前記実施の形態１において図４〜図１２を用いて説明した工程と同様の工程を経ることによって本実施の形態２の半導体装置を製造する。すなわち、実装基板１Ａ上の２箇所の接着材塗布領域のうち、一方の接着材塗布領域に前記実施の形態１で説明したチップ６と同様のチップ６を接着し、他方の接着材塗布領域にチップ（第１半導体チップ）６Ａを接着する。次いで、チップ６上にチップ８を接着する。次いで、実装基板１Ａ上のパッドＰＤ１Ａとチップ６のパッドＰＤ２とをワイヤ９で電気的に接続し、実装基板１Ａ上のパッドＰＤ１Ａとチップ８のパッドＰＤ３とをワイヤ１０で電気的に接続し、実装基板１Ａ上のパッドＰＤ１Ｂとチップ６ＡのパッドＰＤ２Ａとをワイヤ９Ａで電気的に接続する。なお、チップ６上へのチップ８の積層は必要に応じて行うものであり、実装基板１Ａ上に搭載されたチップが単層の状態でも、モールド樹脂１１によって封止してしまってもよい。   Thereafter, the semiconductor device of the second embodiment is manufactured through the same steps as those described in the first embodiment with reference to FIGS. That is, of the two adhesive material application regions on the mounting substrate 1A, the same chip 6 as the chip 6 described in the first embodiment is adhered to one adhesive material application region, and the other adhesive material application region is applied to the other adhesive material application region. A chip (first semiconductor chip) 6A is bonded. Next, the chip 8 is bonded onto the chip 6. Next, the pad PD1A on the mounting substrate 1A and the pad PD2 on the chip 6 are electrically connected by the wire 9, the pad PD1A on the mounting substrate 1A and the pad PD3 on the chip 8 are electrically connected by the wire 10, The pad PD1B on the mounting substrate 1A and the pad PD2A of the chip 6A are electrically connected by a wire 9A. Note that the stacking of the chip 8 on the chip 6 is performed as necessary, and the chip mounted on the mounting substrate 1A may be sealed with the mold resin 11 even in a single layer state.

上記のような本実施の形態２によっても、前記実施の形態１と同様の効果を得ることができる。   According to the second embodiment as described above, the same effect as in the first embodiment can be obtained.

（実施の形態３）
図１７は、本実施の形態３の半導体装置の製造工程中の要部断面図である。 (Embodiment 3)
FIG. 17 is a fragmentary cross-sectional view of the semiconductor device of Third Embodiment during the manufacturing process thereof.

本実施の形態３では、平面で接着材４の残された領域がチップ６より大きくなるようにするものである。すなわち、実装基板１上の接着材塗布領域は、多種のチップを搭載できるように設計されているので、その接着材塗布領域に搭載可能なチップのうち最大のチップの大きさに合わせてマスク３（図１参照）の開口部２（図１参照）を形成しておく。このような開口部２を有するマスク３を用いた場合には、チップ６がその接着材塗布領域と同じサイズでないと接着材４が残る範囲Ｌがチップ６の配置されている範囲Ｐより大きくなるが、前記実施の形態と同様の工程を経ることによって、接着材４がチップ６の側面から這い上がってチップ６の上面に付着してしまったり、接着材４が実装基板１上に広がってパッドＰＤ１に付着してしまう不具合を防ぐことができる。また、接着材４として、ポリイミド系またはエポキシ系の熱硬化性樹脂接着材を選択することによって、後の工程で実装基板１およびチップ６などを樹脂封止した際に、平面でチップ６からはみ出した接着材４とモールド樹脂１１（図１１参照）との接着性が低下してしまう不具合を防ぐことができる。   In the third embodiment, the area where the adhesive 4 is left in a plane is made larger than the chip 6. In other words, the adhesive application area on the mounting substrate 1 is designed so that various types of chips can be mounted. Therefore, the mask 3 is adjusted in accordance with the size of the largest chip among the chips that can be mounted in the adhesive application area. An opening 2 (see FIG. 1) of (see FIG. 1) is formed. When the mask 3 having such an opening 2 is used, the area L where the adhesive 4 remains is larger than the area P where the chip 6 is disposed unless the chip 6 is the same size as the adhesive application area. However, through the same process as in the above-described embodiment, the adhesive 4 crawls up from the side surface of the chip 6 and adheres to the upper surface of the chip 6, or the adhesive 4 spreads on the mounting substrate 1 and is padded. A problem of adhering to PD1 can be prevented. Further, by selecting a polyimide-based or epoxy-based thermosetting resin adhesive as the adhesive 4, when the mounting substrate 1, the chip 6, etc. are resin-sealed in a later process, the surface protrudes from the chip 6 in a plane. It is possible to prevent a problem that the adhesiveness between the adhesive 4 and the mold resin 11 (see FIG. 11) is lowered.

また、本実施の形態３のようにマスク３を形成しておくことにより、チップ６の平面サイズに合わせた開口部２を有するマスク３を準備することなく、実装基板１に異なる種類のチップを接着する場合でも同一のマスク３を用いることが可能となる。それにより、実装基板１に接着するチップの種類毎にマスク３を交換する必要がなくなり、接着材４の塗布条件の再設定も不要になるので、本実施の形態３の半導体装置を短いＴＡＴ（Turn Around Time）で製造できるようになる。また、実装基板１に異なる種類のチップを接着する場合でも同一のマスク３を用いることができることから、実装基板１に異なる種類のチップを接着する場合でも工程を標準化することが可能となる。また、実装基板１に異なる種類のチップを接着する場合でも同一のマスク３を用いることができることから、複数種類のマスク３を形成する必要がなくなるので、本実施の形態３の半導体装置の製造コストを低減することが可能となる。   Further, by forming the mask 3 as in the third embodiment, different types of chips are mounted on the mounting substrate 1 without preparing the mask 3 having the opening 2 that matches the planar size of the chip 6. Even in the case of bonding, the same mask 3 can be used. This eliminates the need to replace the mask 3 for each type of chip to be bonded to the mounting substrate 1 and eliminates the need for resetting the application condition of the adhesive material 4. Therefore, the semiconductor device of the third embodiment can be realized with a short TAT ( It can be manufactured at Turn Around Time. In addition, since the same mask 3 can be used even when different types of chips are bonded to the mounting substrate 1, the process can be standardized even when different types of chips are bonded to the mounting substrate 1. In addition, since the same mask 3 can be used even when different types of chips are bonded to the mounting substrate 1, it is not necessary to form a plurality of types of masks 3. Therefore, the manufacturing cost of the semiconductor device according to the third embodiment is reduced. Can be reduced.

ところで、前記実施の形態２で説明したようなＭＣＭを製造する場合においても、２つのチップ間において実装基板１Ａにパッドが配置されていない場合には、上記のようなマスク３を用いることができる。すなわち、図１８に示すように、２つのチップ６、６Ａの接着される領域を１箇所の接着材塗布領域と見なし、上記マスク３を用いて接着材４の塗布を行うものである。それにより、ＭＣＭを製造する場合でも同一のマスク３を用いることが可能となる。   By the way, also in the case of manufacturing the MCM as described in the second embodiment, the mask 3 as described above can be used when the pad is not arranged on the mounting substrate 1A between the two chips. . That is, as shown in FIG. 18, the area where the two chips 6 and 6A are bonded is regarded as one adhesive material application area, and the adhesive material 4 is applied using the mask 3 described above. This makes it possible to use the same mask 3 even when manufacturing an MCM.

上記の本実施の形態３によっても、前記実施の形態１、２と同様の効果を得ることができる。   According to the third embodiment, the same effects as those of the first and second embodiments can be obtained.

以上、本発明者によってなされた発明を実施の形態に基づき具体的に説明したが、本発明は前記実施の形態に限定されるものではなく、その要旨を逸脱しない範囲で種々変更可能であることはいうまでもない。   As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

たとえば、前記実施の形態においては、Ｓｎ−Ａｇ−Ｃｕ共晶合金から形成されたはんだボールを用いて実装基板にバンプ電極を形成する場合について説明したが、Ｓｎ−Ａｇ−Ｃｕ共晶合金の代わりにＳｎ−Ｐｂ（鉛）共晶合金から形成されたはんだボールを用いてもよい。   For example, in the above-described embodiment, the case where the bump electrode is formed on the mounting substrate using the solder ball formed from the Sn—Ag—Cu eutectic alloy has been described, but instead of the Sn—Ag—Cu eutectic alloy. Alternatively, a solder ball formed from a Sn—Pb (lead) eutectic alloy may be used.

本発明の半導体装置の製造方法は、実装基板上にチップを積層して形成される半導体装置の製造工程に適用することができる。   The semiconductor device manufacturing method of the present invention can be applied to a manufacturing process of a semiconductor device formed by stacking chips on a mounting substrate.

本発明の実施の形態１である半導体装置の製造方法を説明する要部断面図である。It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 1 of this invention. 図１に続く半導体装置の製造工程中の要部断面図である。FIG. 2 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 1; 図２に続く半導体装置の製造工程中の要部断面図である。FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; 図３に続く半導体装置の製造工程中の要部断面図である。FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; 図４に続く半導体装置の製造工程中の要部断面図である。FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; 図５に続く半導体装置の製造工程中の要部断面図である。6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; FIG. 図６に続く半導体装置の製造工程中の要部断面図である。FIG. 7 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 6; 図７に続く半導体装置の製造工程中の要部断面図である。FIG. 8 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 7; 図８に続く半導体装置の製造工程中の要部断面図である。FIG. 9 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 8; 図９に続く半導体装置の製造工程中の要部断面図である。FIG. 10 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 9; 図１０に続く半導体装置の製造工程中の要部断面図である。FIG. 11 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 10; 本発明の実施の形態１である半導体装置の製造工程中の要部断面図である。It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 1 of this invention. 本発明の実施の形態２である半導体装置の製造方法を説明する要部断面図である。It is principal part sectional drawing explaining the manufacturing method of the semiconductor device which is Embodiment 2 of this invention. 図１３に続く半導体装置の製造工程中の要部断面図である。FIG. 14 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 13; 図１４に続く半導体装置の製造工程中の要部断面図である。FIG. 15 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 14; 図１５に続く半導体装置の製造工程中の要部断面図である。FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; 本発明の実施の形態３である半導体装置の製造工程中の要部断面図である。It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 3 of this invention. 本発明の実施の形態３である半導体装置の製造工程中の要部断面図である。It is principal part sectional drawing in the manufacturing process of the semiconductor device which is Embodiment 3 of this invention.

符号の説明Explanation of symbols

１、１Ａ 実装基板
２、２Ａ、２Ｂ 開口部
３、３Ａ、３Ｂ マスク
４ 接着材
５ スキージ
６、６Ａ チップ（第１半導体チップ）
７ 接着材
８ チップ（第２半導体チップ）
９、９Ａ、１０ ワイヤ
１１ モールド樹脂
１２ バンプ電極
１４ チップ
１５ 接着材
１６ ワイヤ
ＨＳ 加熱ステージ
ＰＤ１、ＰＤ１Ａ、ＰＤ１Ｂ パッド
ＰＤ２、ＰＤ２Ａ、ＰＤ３、ＰＤ４ パッド 1, 1A mounting substrate 2, 2A, 2B opening 3, 3A, 3B mask 4 adhesive 5 squeegee 6, 6A chip (first semiconductor chip)
7 Adhesive material 8 Chip (second semiconductor chip)
9, 9A, 10 Wire 11 Mold resin 12 Bump electrode 14 Chip 15 Adhesive 16 Wire HS Heating stage PD1, PD1A, PD1B Pad PD2, PD2A, PD3, PD4 Pad

Claims (5)

（ａ）実装基板の主面に選択的に樹脂接着材を塗布する工程、
（ｂ）前記実装基板に熱処理を施し、前記樹脂接着材を半硬化させる工程、
（ｃ）前記（ｂ）工程後、前記樹脂接着材を介して第１半導体チップを前記樹脂接着材を塗布した領域に接着する工程、
を含むことを特徴とする半導体装置の製造方法。 (A) a step of selectively applying a resin adhesive to the main surface of the mounting substrate;
(B) heat-treating the mounting substrate and semi-curing the resin adhesive;
(C) After the step (b), a step of bonding the first semiconductor chip to the region where the resin adhesive is applied via the resin adhesive,
A method for manufacturing a semiconductor device, comprising: 請求項１記載の半導体装置の製造方法において、
前記（ａ）工程は、
（ａ１）前記樹脂接着材を塗布した領域に対応する開口部を有するマスクを用意する工程、
（ａ２）平面における前記開口部と前記樹脂接着材を塗布した領域の位置を合わせて前記マスクを前記実装基板の前記主面上に配置する工程、
（ａ３）前記（ａ２）工程後、前記開口部上を含む前記マスク上に前記樹脂接着材を塗布する工程、
（ａ４）前記（ａ３）工程後、前記マスクを前記実装基板から取り外し、前記樹脂接着材を塗布した領域に前記樹脂接着材を残す工程、
を含むことを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
The step (a)
(A1) preparing a mask having an opening corresponding to a region where the resin adhesive is applied;
(A2) a step of arranging the mask on the main surface of the mounting substrate by aligning the position of the opening on the plane and the region where the resin adhesive is applied;
(A3) After the step (a2), a step of applying the resin adhesive on the mask including the opening.
(A4) After the step (a3), the step of removing the mask from the mounting substrate and leaving the resin adhesive in a region where the resin adhesive is applied,
A method for manufacturing a semiconductor device, comprising: 請求項１記載の半導体装置の製造方法において、
さらに、
（ｄ）前記（ｃ）工程後、前記実装基板および前記第１半導体チップに熱処理を施す工程、
を有することを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 1,
further,
(D) after the step (c), a step of performing a heat treatment on the mounting substrate and the first semiconductor chip;
A method for manufacturing a semiconductor device, comprising: （ａ）実装基板の主面に選択的に樹脂接着材を塗布する工程、
（ｂ）前記実装基板に熱処理を施し、前記樹脂接着材を半硬化させる工程、
（ｃ）前記（ｂ）工程後、前記樹脂接着材を介して第１半導体チップを前記樹脂接着材を塗布した領域に接着する工程、
（ｄ）裏面にフィルム状接着材が貼付された第２半導体チップを用意する工程、
（ｅ）前記（ｄ）工程後、前記フィルム状接着材を介して前記第２半導体チップを前記第１半導体チップ上に加熱圧着する工程、
を含むことを特徴とする半導体装置の製造方法。 (A) a step of selectively applying a resin adhesive to the main surface of the mounting substrate;
(B) heat-treating the mounting substrate and semi-curing the resin adhesive;
(C) After the step (b), a step of bonding the first semiconductor chip to the region where the resin adhesive is applied via the resin adhesive,
(D) preparing a second semiconductor chip having a film-like adhesive attached to the back surface;
(E) After the step (d), a step of thermocompression bonding the second semiconductor chip onto the first semiconductor chip via the film adhesive,
A method for manufacturing a semiconductor device, comprising: 請求項４記載の半導体装置の製造方法において、
前記（ｄ）工程は、
（ｄ１）その裏面全体に、前記フィルム状接着材が貼り付けられた半導体ウエハを準備する工程と、
（ｄ２）前記半導体ウエハを前記フィルム状接着材とともに分割し、前記第２半導体チップを用意する工程とを含むことを特徴とする半導体装置の製造方法。 In the manufacturing method of the semiconductor device according to claim 4,
The step (d)
(D1) a step of preparing a semiconductor wafer having the film adhesive adhered to the entire back surface;
(D2) dividing the semiconductor wafer together with the film adhesive, and preparing the second semiconductor chip.
JP2003333620A 2003-09-25 2003-09-25 Manufacturing method of semiconductor device Pending JP2005101312A (en)

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JP2011135102A (en) * 2011-03-23 2011-07-07 Renesas Electronics Corp Semiconductor device
JP2012015554A (en) * 2011-10-17 2012-01-19 Renesas Electronics Corp Semiconductor device manufacturing method and multilayer semiconductor device manufacturing method
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Publication number Priority date Publication date Assignee Title
JP2008509572A (en) * 2004-08-13 2008-03-27 インテル コーポレイション Method and apparatus for attaching a die in a stacked die package
JP4732456B2 (en) * 2004-08-13 2011-07-27 インテル コーポレイション Method and apparatus for attaching a die in a stacked die package
JP2011135102A (en) * 2011-03-23 2011-07-07 Renesas Electronics Corp Semiconductor device
JP2012015554A (en) * 2011-10-17 2012-01-19 Renesas Electronics Corp Semiconductor device manufacturing method and multilayer semiconductor device manufacturing method
US9252126B2 (en) 2012-04-02 2016-02-02 Ps4 Luxco S.A.R.L. Multi Chip Package-type semiconductor device

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