JP2005101312A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP2005101312A
JP2005101312A JP2003333620A JP2003333620A JP2005101312A JP 2005101312 A JP2005101312 A JP 2005101312A JP 2003333620 A JP2003333620 A JP 2003333620A JP 2003333620 A JP2003333620 A JP 2003333620A JP 2005101312 A JP2005101312 A JP 2005101312A
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Japan
Prior art keywords
chip
adhesive
mounting substrate
semiconductor device
mask
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Pending
Application number
JP2003333620A
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English (en)
Japanese (ja)
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JP2005101312A5 (enExample
Inventor
Tomoko Tono
朋子 東野
Kazunari Suzuki
一成 鈴木
Toshihiro Shiotsuki
敏弘 塩月
Hideyuki Suga
秀幸 須賀
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
Original Assignee
Renesas Technology Corp
Renesas Eastern Japan Semiconductor Inc
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Application filed by Renesas Technology Corp, Renesas Eastern Japan Semiconductor Inc filed Critical Renesas Technology Corp
Priority to JP2003333620A priority Critical patent/JP2005101312A/ja
Publication of JP2005101312A publication Critical patent/JP2005101312A/ja
Publication of JP2005101312A5 publication Critical patent/JP2005101312A5/ja
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/27—Manufacturing methods
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    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
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    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
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    • H01L2924/181—Encapsulation

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
JP2003333620A 2003-09-25 2003-09-25 半導体装置の製造方法 Pending JP2005101312A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003333620A JP2005101312A (ja) 2003-09-25 2003-09-25 半導体装置の製造方法

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Application Number Priority Date Filing Date Title
JP2003333620A JP2005101312A (ja) 2003-09-25 2003-09-25 半導体装置の製造方法

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JP2005101312A true JP2005101312A (ja) 2005-04-14
JP2005101312A5 JP2005101312A5 (enExample) 2006-11-09

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008509572A (ja) * 2004-08-13 2008-03-27 インテル コーポレイション スタックダイパッケージにおいてダイを取り付ける方法及び装置
JP2011135102A (ja) * 2011-03-23 2011-07-07 Renesas Electronics Corp 半導体装置
JP2012015554A (ja) * 2011-10-17 2012-01-19 Renesas Electronics Corp 半導体装置の製造方法、および積層型半導体装置の製造方法
US9252126B2 (en) 2012-04-02 2016-02-02 Ps4 Luxco S.A.R.L. Multi Chip Package-type semiconductor device

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01253244A (ja) * 1988-04-01 1989-10-09 Toshiba Chem Corp 半導体装置の製造方法
JPH02177553A (ja) * 1988-12-28 1990-07-10 Matsushita Electric Ind Co Ltd 集積回路装置およびその製造方法
JP2001338932A (ja) * 2000-05-29 2001-12-07 Canon Inc 半導体装置及び半導体装置の製造方法
JP2003264205A (ja) * 2002-03-08 2003-09-19 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01253244A (ja) * 1988-04-01 1989-10-09 Toshiba Chem Corp 半導体装置の製造方法
JPH02177553A (ja) * 1988-12-28 1990-07-10 Matsushita Electric Ind Co Ltd 集積回路装置およびその製造方法
JP2001338932A (ja) * 2000-05-29 2001-12-07 Canon Inc 半導体装置及び半導体装置の製造方法
JP2003264205A (ja) * 2002-03-08 2003-09-19 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008509572A (ja) * 2004-08-13 2008-03-27 インテル コーポレイション スタックダイパッケージにおいてダイを取り付ける方法及び装置
JP2011135102A (ja) * 2011-03-23 2011-07-07 Renesas Electronics Corp 半導体装置
JP2012015554A (ja) * 2011-10-17 2012-01-19 Renesas Electronics Corp 半導体装置の製造方法、および積層型半導体装置の製造方法
US9252126B2 (en) 2012-04-02 2016-02-02 Ps4 Luxco S.A.R.L. Multi Chip Package-type semiconductor device

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