JP2005072566A5 - - Google Patents

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Publication number
JP2005072566A5
JP2005072566A5 JP2004217318A JP2004217318A JP2005072566A5 JP 2005072566 A5 JP2005072566 A5 JP 2005072566A5 JP 2004217318 A JP2004217318 A JP 2004217318A JP 2004217318 A JP2004217318 A JP 2004217318A JP 2005072566 A5 JP2005072566 A5 JP 2005072566A5
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JP
Japan
Prior art keywords
well
conductivity type
mos transistor
semiconductor substrate
wells
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Application number
JP2004217318A
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English (en)
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JP5079974B2 (ja
JP2005072566A (ja
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Priority to JP2004217318A priority Critical patent/JP5079974B2/ja
Priority claimed from JP2004217318A external-priority patent/JP5079974B2/ja
Publication of JP2005072566A publication Critical patent/JP2005072566A/ja
Publication of JP2005072566A5 publication Critical patent/JP2005072566A5/ja
Application granted granted Critical
Publication of JP5079974B2 publication Critical patent/JP5079974B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Claims (3)

  1. 第１導電型の半導体基板と、前記半導体基板の表面に互いに離間して形成された第２導電型の第１及び第２のウェルと、前記第１のウェル内に形成された第１導電型の第３のウェルと、前記第２のウェル内に形成された第２導電型の第４のウェルと、前記第３のウェルの表面に形成された第２導電チャンネル型ＭＯＳトランジスタと、前記第４のウェルの表面に形成された第１導電チャンネル型ＭＯＳトランジスタと、を有することを特徴とする半導体装置。
  2. 第１導電型の半導体基板と、前記半導体基板の表面に互いに離間して形成された第２導電型の第１及び第２のウェルと、前記第１のウェル内に形成された第１導電型の第３のウェルと、前記第３のウェルの表面に形成された第２導電チャンネル型ＭＯＳトランジスタと、前記第２のウェルの表面に形成された第１導電チャンネル型ＭＯＳトランジスタと、を有することを特徴とする半導体装置。
  3. 前記第１のウェルと前記第２のウェルが同電位にバイアスされたことを特徴とする請求項１または請求項２に記載の半導体装置。
JP2004217318A 2003-08-06 2004-07-26 半導体装置 Expired - Fee Related JP5079974B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2004217318A JP5079974B2 (ja) 2003-08-06 2004-07-26 半導体装置

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP2003288153 2003-08-06
JP2003288153 2003-08-06
JP2004217318A JP5079974B2 (ja) 2003-08-06 2004-07-26 半導体装置

Publications (3)

Publication Number Publication Date
JP2005072566A JP2005072566A (ja) 2005-03-17
JP2005072566A5 true JP2005072566A5 (ja) 2007-08-09
JP5079974B2 JP5079974B2 (ja) 2012-11-21

Family

ID=34213282

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004217318A Expired - Fee Related JP5079974B2 (ja) 2003-08-06 2004-07-26 半導体装置

Country Status (5)

Country Link
US (1) US7345345B2 (ja)
JP (1) JP5079974B2 (ja)
KR (1) KR100749231B1 (ja)
CN (1) CN100435240C (ja)
TW (1) TWI256724B (ja)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4530823B2 (ja) 2004-12-02 2010-08-25 三洋電機株式会社 半導体装置及びその製造方法
US20070041144A1 (en) * 2005-05-23 2007-02-22 Clement Szeto Method for reducing substrate noise from penetrating noise sensitive circuits
CN101238580B (zh) * 2005-08-18 2010-06-16 富士通微电子株式会社 半导体器件及其制造方法
KR100688588B1 (ko) 2006-02-27 2007-03-02 삼성전자주식회사 래치-업의 발생을 방지할 수 있는 ｃｍｏｓ 반도체 장치
JP5036234B2 (ja) 2006-07-07 2012-09-26 三菱電機株式会社 半導体装置
US7847581B2 (en) * 2008-04-03 2010-12-07 Stmicroelectronics (Rousset) Sas Device for protecting an integrated circuit against a laser attack
JP5259246B2 (ja) * 2008-05-09 2013-08-07 ルネサスエレクトロニクス株式会社 半導体装置
DE102008047850B4 (de) * 2008-09-18 2015-08-20 Austriamicrosystems Ag Halbleiterkörper mit einer Schutzstruktur und Verfahren zum Herstellen derselben
JP5896682B2 (ja) 2011-10-18 2016-03-30 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9287253B2 (en) * 2011-11-04 2016-03-15 Synopsys, Inc. Method and apparatus for floating or applying voltage to a well of an integrated circuit
JP5725230B2 (ja) * 2014-04-09 2015-05-27 株式会社デンソー 半導体装置
JP6118923B2 (ja) * 2016-01-26 2017-04-19 ルネサスエレクトロニクス株式会社 半導体集積回路装置
US9633992B1 (en) * 2016-02-23 2017-04-25 Vanguard International Semiconductor Corporation Electrostatic discharge protection device
CN108878417B (zh) * 2018-07-05 2020-10-30 江南大学 一种高维持mos辅助触发scr结构的瞬态电压抑制器
KR102482194B1 (ko) * 2018-08-24 2022-12-27 삼성전기주식회사 삽입손실이 개선된 cmos 트랜지스터의 배치 구조
CN110534512B (zh) * 2019-09-07 2023-02-07 电子科技大学 一种抗闩锁版图结构

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62155555A (ja) * 1985-09-18 1987-07-10 Sony Corp 相補型ｍｏｓトランジスタ
US4761571A (en) * 1985-12-19 1988-08-02 Honeywell Inc. Memory circuit enchancement to stablize the signal lines with additional capacitance
JPH05326862A (ja) * 1992-05-14 1993-12-10 Fujitsu Ltd 半導体装置
KR940003026A (ko) * 1992-07-13 1994-02-19 김광호 트리플웰을 이용한 반도체장치
JPH06232355A (ja) * 1993-02-02 1994-08-19 Hitachi Ltd Ｍｏｓ半導体製造装置
JPH08149011A (ja) * 1994-11-18 1996-06-07 Mitsubishi Electric Corp 電流加算型ディジタル／アナログ変換器
JP3419672B2 (ja) * 1997-12-19 2003-06-23 富士通株式会社 半導体装置及びその製造方法
JP3196714B2 (ja) * 1998-03-05 2001-08-06 日本電気株式会社 トリプルウェル構造の半導体集積回路の製造方法
JP2000101045A (ja) * 1998-07-23 2000-04-07 Mitsubishi Electric Corp 半導体装置
KR20000041323A (ko) * 1998-12-22 2000-07-15 윤종용 트리플 웰 구조를 갖는 반도체 장치의 제조 방법
US6432761B1 (en) * 1999-10-01 2002-08-13 Microchip Technology Incorporated Apparatus and method for independent threshold voltage control of memory cell and select gate in a split-EEPROM
US6376870B1 (en) * 2000-09-08 2002-04-23 Texas Instruments Incorporated Low voltage transistors with increased breakdown voltage to substrate
JP2002222869A (ja) 2001-01-23 2002-08-09 Fuji Electric Co Ltd 半導体集積回路装置およびその製造方法
US6791883B2 (en) * 2002-06-24 2004-09-14 Freescale Semiconductor, Inc. Program and erase in a thin film storage non-volatile memory

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