JP2004213830A - 半導体記憶装置 - Google Patents

半導体記憶装置 Download PDF

Info

Publication number
JP2004213830A
JP2004213830A JP2003002472A JP2003002472A JP2004213830A JP 2004213830 A JP2004213830 A JP 2004213830A JP 2003002472 A JP2003002472 A JP 2003002472A JP 2003002472 A JP2003002472 A JP 2003002472A JP 2004213830 A JP2004213830 A JP 2004213830A
Authority
JP
Japan
Prior art keywords
column
write
memory cell
writing
bit line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003002472A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004213830A5 (enExample
Inventor
Kenichi Shigenami
賢一 重並
Shunichi Sukegawa
俊一 助川
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP2003002472A priority Critical patent/JP2004213830A/ja
Priority to US10/749,559 priority patent/US7012831B2/en
Publication of JP2004213830A publication Critical patent/JP2004213830A/ja
Publication of JP2004213830A5 publication Critical patent/JP2004213830A5/ja
Pending legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40603Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40622Partial refresh of memory arrays
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
JP2003002472A 2003-01-08 2003-01-08 半導体記憶装置 Pending JP2004213830A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2003002472A JP2004213830A (ja) 2003-01-08 2003-01-08 半導体記憶装置
US10/749,559 US7012831B2 (en) 2003-01-08 2004-01-02 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2003002472A JP2004213830A (ja) 2003-01-08 2003-01-08 半導体記憶装置

Publications (2)

Publication Number Publication Date
JP2004213830A true JP2004213830A (ja) 2004-07-29
JP2004213830A5 JP2004213830A5 (enExample) 2005-04-07

Family

ID=32820205

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003002472A Pending JP2004213830A (ja) 2003-01-08 2003-01-08 半導体記憶装置

Country Status (2)

Country Link
US (1) US7012831B2 (enExample)
JP (1) JP2004213830A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007257682A (ja) * 2006-03-20 2007-10-04 Sony Corp 半導体メモリデバイスとその動作方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7375999B2 (en) * 2005-09-29 2008-05-20 Infineon Technologies Ag Low equalized sense-amp for twin cell DRAMs
KR100780613B1 (ko) * 2006-06-30 2007-11-29 주식회사 하이닉스반도체 반도체 메모리 소자 및 그 구동방법
DE102007042879B3 (de) * 2007-09-08 2009-06-10 Qimonda Ag Speichervorrichtung mit Bewertungsschaltung für die elektrische Ladung einer Speicherzelle
KR101975528B1 (ko) 2012-07-17 2019-05-07 삼성전자주식회사 패스트 어레이 영역을 갖는 반도체 메모리 셀 어레이 및 그것을 포함하는 반도체 메모리
US20140146589A1 (en) * 2012-11-29 2014-05-29 Samsung Electronics Co., Ltd. Semiconductor memory device with cache function in dram
US9324414B2 (en) * 2013-07-24 2016-04-26 Stmicroelectronics International N.V. Selective dual cycle write operation for a self-timed memory
US9711206B2 (en) * 2014-06-05 2017-07-18 Micron Technology, Inc. Performing logical operations using sensing circuitry
KR20160063726A (ko) * 2014-11-27 2016-06-07 에스케이하이닉스 주식회사 메모리 장치 및 이를 포함하는 메모리 시스템
KR20180058478A (ko) * 2016-11-24 2018-06-01 에스케이하이닉스 주식회사 반도체 장치, 이를 포함하는 반도체 시스템 및 반도체 장치의 리드 및 라이트 동작 방법
US11605421B2 (en) * 2020-07-17 2023-03-14 Micron Technology, Inc. Semiconductor device having driver circuits and sense amplifiers

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943944A (en) * 1987-11-25 1990-07-24 Kabushiki Kaisha Toshiba Semiconductor memory using dynamic ram cells
JPH01143094A (ja) * 1987-11-28 1989-06-05 Mitsubishi Electric Corp 半導体記憶装置
JP3101298B2 (ja) * 1990-03-30 2000-10-23 株式会社東芝 半導体メモリ装置
JP3101297B2 (ja) * 1990-03-30 2000-10-23 株式会社東芝 半導体メモリ装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007257682A (ja) * 2006-03-20 2007-10-04 Sony Corp 半導体メモリデバイスとその動作方法

Also Published As

Publication number Publication date
US7012831B2 (en) 2006-03-14
US20040190326A1 (en) 2004-09-30

Similar Documents

Publication Publication Date Title
JP4531886B2 (ja) 強誘電体メモリ装置
US6552944B2 (en) Single bitline direct sensing architecture for high speed memory device
JP3183076B2 (ja) 強誘電体メモリ装置
KR100276569B1 (ko) 강유전메모리장치
CN102956262B (zh) 静态ram
JP4331484B2 (ja) ランダムアクセスメモリ及びその読み出し、書き込み、及びリフレッシュ方法
US20020176302A1 (en) Cell data protection circuit in semiconductor memory device and method of driving refresh mode
JPH0352187A (ja) ダイナミック型ランダムアクセスメモリ
US6320806B1 (en) Input/output line precharge circuit and semiconductor memory device adopting the same
KR0184092B1 (ko) 다이나믹형 메모리
US8451675B2 (en) Methods for accessing DRAM cells using separate bit line control
JP2004213830A (ja) 半導体記憶装置
JPH04318391A (ja) 半導体記憶装置
US20090021995A1 (en) Early Write Method and Apparatus
JP3980417B2 (ja) 集積回路メモリ
JP2003297078A (ja) 強誘電体メモリ装置
JP2011118975A (ja) 半導体記憶装置
JPH04184787A (ja) ダイナミック型半導体記憶装置
US6137715A (en) Static random access memory with rewriting circuit
JP3906178B2 (ja) 強誘電体メモリ
US6674685B2 (en) Semiconductor memory device having write column select gate
JP2007134012A (ja) 半導体記憶装置および半導体記憶装置の駆動方法
US6643214B2 (en) Semiconductor memory device having write column select gate
US8681574B2 (en) Separate pass gate controlled sense amplifier
KR101171254B1 (ko) 비트라인 센스앰프 제어 회로 및 이를 구비하는 반도체 메모리 장치

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040426

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040426

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060808

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061010

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070619

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20071127