JP2004213830A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP2004213830A JP2004213830A JP2003002472A JP2003002472A JP2004213830A JP 2004213830 A JP2004213830 A JP 2004213830A JP 2003002472 A JP2003002472 A JP 2003002472A JP 2003002472 A JP2003002472 A JP 2003002472A JP 2004213830 A JP2004213830 A JP 2004213830A
- Authority
- JP
- Japan
- Prior art keywords
- column
- write
- memory cell
- writing
- bit line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40603—Arbitration, priority and concurrent access to memory cells for read/write or refresh operations
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003002472A JP2004213830A (ja) | 2003-01-08 | 2003-01-08 | 半導体記憶装置 |
| US10/749,559 US7012831B2 (en) | 2003-01-08 | 2004-01-02 | Semiconductor memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003002472A JP2004213830A (ja) | 2003-01-08 | 2003-01-08 | 半導体記憶装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004213830A true JP2004213830A (ja) | 2004-07-29 |
| JP2004213830A5 JP2004213830A5 (enExample) | 2005-04-07 |
Family
ID=32820205
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2003002472A Pending JP2004213830A (ja) | 2003-01-08 | 2003-01-08 | 半導体記憶装置 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US7012831B2 (enExample) |
| JP (1) | JP2004213830A (enExample) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007257682A (ja) * | 2006-03-20 | 2007-10-04 | Sony Corp | 半導体メモリデバイスとその動作方法 |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7375999B2 (en) * | 2005-09-29 | 2008-05-20 | Infineon Technologies Ag | Low equalized sense-amp for twin cell DRAMs |
| KR100780613B1 (ko) * | 2006-06-30 | 2007-11-29 | 주식회사 하이닉스반도체 | 반도체 메모리 소자 및 그 구동방법 |
| DE102007042879B3 (de) * | 2007-09-08 | 2009-06-10 | Qimonda Ag | Speichervorrichtung mit Bewertungsschaltung für die elektrische Ladung einer Speicherzelle |
| KR101975528B1 (ko) | 2012-07-17 | 2019-05-07 | 삼성전자주식회사 | 패스트 어레이 영역을 갖는 반도체 메모리 셀 어레이 및 그것을 포함하는 반도체 메모리 |
| US20140146589A1 (en) * | 2012-11-29 | 2014-05-29 | Samsung Electronics Co., Ltd. | Semiconductor memory device with cache function in dram |
| US9324414B2 (en) * | 2013-07-24 | 2016-04-26 | Stmicroelectronics International N.V. | Selective dual cycle write operation for a self-timed memory |
| US9711206B2 (en) * | 2014-06-05 | 2017-07-18 | Micron Technology, Inc. | Performing logical operations using sensing circuitry |
| KR20160063726A (ko) * | 2014-11-27 | 2016-06-07 | 에스케이하이닉스 주식회사 | 메모리 장치 및 이를 포함하는 메모리 시스템 |
| KR20180058478A (ko) * | 2016-11-24 | 2018-06-01 | 에스케이하이닉스 주식회사 | 반도체 장치, 이를 포함하는 반도체 시스템 및 반도체 장치의 리드 및 라이트 동작 방법 |
| US11605421B2 (en) * | 2020-07-17 | 2023-03-14 | Micron Technology, Inc. | Semiconductor device having driver circuits and sense amplifiers |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4943944A (en) * | 1987-11-25 | 1990-07-24 | Kabushiki Kaisha Toshiba | Semiconductor memory using dynamic ram cells |
| JPH01143094A (ja) * | 1987-11-28 | 1989-06-05 | Mitsubishi Electric Corp | 半導体記憶装置 |
| JP3101298B2 (ja) * | 1990-03-30 | 2000-10-23 | 株式会社東芝 | 半導体メモリ装置 |
| JP3101297B2 (ja) * | 1990-03-30 | 2000-10-23 | 株式会社東芝 | 半導体メモリ装置 |
-
2003
- 2003-01-08 JP JP2003002472A patent/JP2004213830A/ja active Pending
-
2004
- 2004-01-02 US US10/749,559 patent/US7012831B2/en not_active Expired - Lifetime
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007257682A (ja) * | 2006-03-20 | 2007-10-04 | Sony Corp | 半導体メモリデバイスとその動作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| US7012831B2 (en) | 2006-03-14 |
| US20040190326A1 (en) | 2004-09-30 |
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| Date | Code | Title | Description |
|---|---|---|---|
| A521 | Request for written amendment filed |
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| A621 | Written request for application examination |
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| A02 | Decision of refusal |
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