JP2004080060A - 電子部品用パッケージ及びその製造方法 - Google Patents
電子部品用パッケージ及びその製造方法 Download PDFInfo
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- JP2004080060A JP2004080060A JP2003400508A JP2003400508A JP2004080060A JP 2004080060 A JP2004080060 A JP 2004080060A JP 2003400508 A JP2003400508 A JP 2003400508A JP 2003400508 A JP2003400508 A JP 2003400508A JP 2004080060 A JP2004080060 A JP 2004080060A
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- Prior art keywords
- plating
- thickness
- package
- plating layer
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- Electroplating Methods And Accessories (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
【解決手段】 1回目にかけられるニッケルメッキ層31の厚さを1.5〜2.5μmとした。1回目のNiメッキ層31の厚さを1.5μm以上と厚くしたため、放熱部材21の銅の1回目のNiメッキ層31への拡散があっても、その表面に存在するCu−Ni合金層を少なくできる。したがって、2回目のNiメッキ層32の密着性の低下が小さくなり、フクレの発生も防止される。1回目のNiメッキ層31の厚さの上限を2.5μmとしたため、同Niメッキ自体の密着性の低下もない。
【選択図】 図1
Description
2,42 パッケージ本体
4 メタライズ層
7 貫通孔
21,51 放熱部材
31,32 Niメッキ層
33 Auメッキ層
S 電子部品
Claims (4)
- パッケージ本体に銅又は銅合金からなる放熱部材が接合され、該放熱部材に、ニッケルメッキが複数回かけられてなる電子部品用パッケージにおいて、
1回目にかけられるニッケルメッキ層の厚さを1.5〜2.5μmとしたことを特徴とする電子部品用パッケージ。 - パッケージ本体に銅又は銅合金からなる放熱部材が接合され、該放熱部材に、ニッケルメッキが複数回かけられてなる電子部品用パッケージにおいて、
1回目にかけられるニッケルメッキ層の厚さを1.5〜2.0μmとしたことを特徴とする電子部品用パッケージ。 - パッケージ本体に銅又は銅合金からなる放熱部材を接合した後、該放熱部材を含む金属面に、ニッケルメッキをかけ、その後、加熱処理して再度ニッケルメッキをかけることで電子部品用パッケージを製造する方法において、
1回目にかけるニッケルメッキ層の厚さを1.5〜2.5μmとしたことを特徴とする電子部品用パッケージの製造方法。 - パッケージ本体に銅又は銅合金からなる放熱部材を接合した後、該放熱部材を含む金属面に、ニッケルメッキをかけ、その後、加熱処理して再度ニッケルメッキをかけることで電子部品用パッケージを製造する方法において、
1回目にかけるニッケルメッキ層の厚さを1.5〜2.0μmとしたことを特徴とする電子部品用パッケージの製造方法。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003400508A JP4663975B2 (ja) | 2003-11-28 | 2003-11-28 | 電子部品用パッケージ |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003400508A JP4663975B2 (ja) | 2003-11-28 | 2003-11-28 | 電子部品用パッケージ |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP29447398A Division JP3512653B2 (ja) | 1998-09-30 | 1998-09-30 | 電子部品用パッケージの製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2004080060A true JP2004080060A (ja) | 2004-03-11 |
JP2004080060A5 JP2004080060A5 (ja) | 2005-12-22 |
JP4663975B2 JP4663975B2 (ja) | 2011-04-06 |
Family
ID=32025987
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003400508A Expired - Fee Related JP4663975B2 (ja) | 2003-11-28 | 2003-11-28 | 電子部品用パッケージ |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4663975B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006028208A1 (ja) * | 2004-09-10 | 2006-03-16 | Mitsui Mining & Smelting Co., Ltd. | キャパシタ層形成材及びキャパシタ層形成材を用いて得られる内蔵キャパシタ回路を備えるプリント配線板 |
JP2007123566A (ja) * | 2005-10-28 | 2007-05-17 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
US20080298024A1 (en) * | 2007-05-31 | 2008-12-04 | A.L.M.T. Corp. | Heat spreader and method for manufacturing the same, and semiconductor device |
JP2013123011A (ja) * | 2011-12-12 | 2013-06-20 | Denso Corp | 電子装置 |
-
2003
- 2003-11-28 JP JP2003400508A patent/JP4663975B2/ja not_active Expired - Fee Related
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2006028208A1 (ja) * | 2004-09-10 | 2006-03-16 | Mitsui Mining & Smelting Co., Ltd. | キャパシタ層形成材及びキャパシタ層形成材を用いて得られる内蔵キャパシタ回路を備えるプリント配線板 |
JP2006080401A (ja) * | 2004-09-10 | 2006-03-23 | Mitsui Mining & Smelting Co Ltd | キャパシタ層形成材及びキャパシタ層形成材を用いて得られる内蔵キャパシタ回路を備えるプリント配線板。 |
KR100844258B1 (ko) * | 2004-09-10 | 2008-07-07 | 미쓰이 긴조꾸 고교 가부시키가이샤 | 커패시터층 형성재 및 커패시터층 형성재를 이용하여얻어지는 내장 커패시터 회로를 구비하는 프린트 배선판 |
US7430106B2 (en) | 2004-09-10 | 2008-09-30 | Mitsui Mining & Smelting Co., Ltd. | Materials for forming capacitor layer and printed wiring board having embedded capacitor circuit obtained by using the same |
JP2007123566A (ja) * | 2005-10-28 | 2007-05-17 | Fuji Electric Holdings Co Ltd | 半導体装置およびその製造方法 |
US20080298024A1 (en) * | 2007-05-31 | 2008-12-04 | A.L.M.T. Corp. | Heat spreader and method for manufacturing the same, and semiconductor device |
JP2013123011A (ja) * | 2011-12-12 | 2013-06-20 | Denso Corp | 電子装置 |
Also Published As
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JP4663975B2 (ja) | 2011-04-06 |
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