JP2004048013A - エレクトロニクスユニット及びその製造方法 - Google Patents

エレクトロニクスユニット及びその製造方法 Download PDF

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Publication number
JP2004048013A
JP2004048013A JP2003193666A JP2003193666A JP2004048013A JP 2004048013 A JP2004048013 A JP 2004048013A JP 2003193666 A JP2003193666 A JP 2003193666A JP 2003193666 A JP2003193666 A JP 2003193666A JP 2004048013 A JP2004048013 A JP 2004048013A
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JP
Japan
Prior art keywords
track system
conductor track
electronic unit
layer
support
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2003193666A
Other languages
English (en)
Japanese (ja)
Other versions
JP2004048013A5 (enExample
Inventor
Waldemar Brinkis
ヴァルデマー　ブリンキス
Erich Mattmann
エーリッヒ　マットマン
Bernd Thyzel
ベルント　テューツェル
Klaus Weber
クラウス　ヴェーバー
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of JP2004048013A publication Critical patent/JP2004048013A/ja
Publication of JP2004048013A5 publication Critical patent/JP2004048013A5/ja
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142—Metallic substrates having insulating layers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
JP2003193666A 2002-07-08 2003-07-08 エレクトロニクスユニット及びその製造方法 Pending JP2004048013A (ja)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE10230712A DE10230712B4 (de) 2002-07-08 2002-07-08 Elektronikeinheit mit einem niedrigschmelzenden metallischen Träger

Publications (2)

Publication Number Publication Date
JP2004048013A true JP2004048013A (ja) 2004-02-12
JP2004048013A5 JP2004048013A5 (enExample) 2006-06-08

Family

ID=30128082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003193666A Pending JP2004048013A (ja) 2002-07-08 2003-07-08 エレクトロニクスユニット及びその製造方法

Country Status (3)

Country Link
US (1) US7453145B2 (enExample)
JP (1) JP2004048013A (enExample)
DE (1) DE10230712B4 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4711792B2 (ja) * 2005-09-26 2011-06-29 三洋電機株式会社 回路装置
US7772036B2 (en) * 2006-04-06 2010-08-10 Freescale Semiconductor, Inc. Lead frame based, over-molded semiconductor package with integrated through hole technology (THT) heat spreader pin(s) and associated method of manufacturing
DE102019215793A1 (de) 2019-10-14 2021-04-15 Vitesco Technologies GmbH Verdrahtungssubstrat für ein Halbleiterbauteil und Verfahren zur Herstellung eines Verdrahtungssubstrats

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05136304A (ja) * 1991-11-14 1993-06-01 Mitsubishi Electric Corp 半導体モジユール及びそれを用いたパワー制御装置
JPH05183314A (ja) * 1991-10-25 1993-07-23 Tdk Corp 多層セラミック部品の製造方法および多層セラミック部品
JP2001185851A (ja) * 1999-12-24 2001-07-06 Kyocera Corp 多層基板の製法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL6705522A (enExample) * 1967-04-20 1968-10-21
US3714709A (en) * 1970-07-06 1973-02-06 Rca Corp Method of manufacturing thick-film hybrid integrated circuits
JPS5933894A (ja) * 1982-08-19 1984-02-23 電気化学工業株式会社 混成集積用回路基板の製造法
US4724040A (en) * 1986-01-14 1988-02-09 Asahi Chemical Research Laboratory Co., Ltd. Method for producing electric circuits on a base boad
JPH0812801B2 (ja) * 1988-01-11 1996-02-07 株式会社日立製作所 ハイブリットｉｃ用基板とそれを用いたハイブリットｉｃ及びその装置
JPH0325996A (ja) 1989-06-23 1991-02-04 Nitto Boseki Co Ltd 射出成形プリント配線板用転写シート及びその製造方法
DE4129835A1 (de) * 1991-09-07 1993-03-11 Bosch Gmbh Robert Leistungselektroniksubstrat und verfahren zu dessen herstellung
JP2677735B2 (ja) * 1992-05-22 1997-11-17 三菱電機株式会社 混成集積回路装置
DE4427112A1 (de) * 1994-07-30 1996-02-01 Kolbe & Co Hans Leiterplattenanordnung
JPH09246001A (ja) * 1996-03-08 1997-09-19 Matsushita Electric Ind Co Ltd 抵抗組成物およびこれを用いた抵抗器
DE19700963C2 (de) 1997-01-14 2000-12-21 Telefunken Microelectron Verfahren zur Herstellung eines Leistungsmoduls mit einer aktive Halbleiterbauelemente und passive Halbleiterbauelemente aufweisenden Schaltungsanordnung
US6617671B1 (en) * 1999-06-10 2003-09-09 Micron Technology, Inc. High density stackable and flexible substrate-based semiconductor device modules
JP3932327B2 (ja) * 2000-09-26 2007-06-20 綜研化学株式会社 ペースト状無機粉体樹脂組成物及びその焼結体の形成方法
DE10118384A1 (de) * 2001-04-12 2002-10-24 Siemens Ag Anordnung zur Kühlung eines Leistungs-Halbleiterelementes

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05183314A (ja) * 1991-10-25 1993-07-23 Tdk Corp 多層セラミック部品の製造方法および多層セラミック部品
JPH05136304A (ja) * 1991-11-14 1993-06-01 Mitsubishi Electric Corp 半導体モジユール及びそれを用いたパワー制御装置
JP2001185851A (ja) * 1999-12-24 2001-07-06 Kyocera Corp 多層基板の製法

Also Published As

Publication number Publication date
DE10230712A1 (de) 2004-02-12
US20050254220A1 (en) 2005-11-17
US7453145B2 (en) 2008-11-18
DE10230712B4 (de) 2006-03-23

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