JP2004039225A - フラッシュメモリ素子におけるトリムビット信号生成回路 - Google Patents
フラッシュメモリ素子におけるトリムビット信号生成回路 Download PDFInfo
- Publication number
- JP2004039225A JP2004039225A JP2003271035A JP2003271035A JP2004039225A JP 2004039225 A JP2004039225 A JP 2004039225A JP 2003271035 A JP2003271035 A JP 2003271035A JP 2003271035 A JP2003271035 A JP 2003271035A JP 2004039225 A JP2004039225 A JP 2004039225A
- Authority
- JP
- Japan
- Prior art keywords
- trim bit
- signal
- trim
- node
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/20—Initialising; Data preset; Chip identification
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
- G11C29/785—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes
- G11C29/789—Masking faults in memories by using spares or by reconfiguring using programmable devices with redundancy programming schemes using non-volatile cells or latches
Abstract
メモリセルを用いてトリムビット信号を生成することにより、半導体メモリ素子のパッケージング以後にも状況に応じてトリムビットを復旧することが可能なトリムビット生成回路を提供する。
【解決手段】
トリムビット選択信号を入力され、トリムビット選択信号によって選択されて、書込み可能及び消去可能なメモリセルを含む制御部と、前記制御部の前記メモリセルの状態に応じてトリムビット信号出力端子からハイレベル信号又はローレベル信号を出力する出力部とを備えてなる。
【選択図】 図3
Description
P0 … PMOSトランジスタ
N0〜N2 … NMOSトランジスタ
Claims (4)
- フラッシュメモリ素子におけるトリムビット信号生成回路であって、
トリムビット選択信号を入力され、前記トリムビット選択信号によって選択されて、書込み可能及び消去可能なメモリセルを含む制御部と、
前記制御部の前記メモリセルの状態に応じてトリムビット信号出力端子からハイレベル信号又はローレベル信号を出力する出力部と
を備えてなるトリムビット信号生成回路。 - 請求項1に記載のトリムビット信号生成回路において、
前記制御部は、
前記トリムビット選択信号を反転させる第1インバータと、
前記第1インバータの出力と第1ノードとの間に接続され、第1制御信号に応じてターンオンされる第1スイッチング素子と、
前記第1ノードと第2ノードとの間に接続され、第2制御信号に応じて動作する前記メモリセルと、
前記第2ノードと前記制御部の出力との間に接続され、第3制御信号に応じてターンオンされる第2スイッチング素子と、
前記第1ノードと接地との間に接続され、第4制御信号に応じてターンオンされる第3スイッチング素子とを含んでなる
ことを特徴とするトリムビット信号生成回路。 - 請求項2に記載のトリムビット信号生成回路において、
前記第1、第2及び第3スイッチング素子のそれぞれがトランジスタからなる
ことを特徴とするトリムビット信号生成回路。 - 請求項1に記載のトリムビット信号生成回路において、
前記出力部は、
電源と前記制御部の出力との間に接続され、ゲート端子が接地されるPMOSトランジスタと、
前記制御部の出力と前記トリムビット信号出力端子との間に直列接続された第1及び第2インバータを含んでなる
ことを特徴とするトリムビット信号生成回路。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP04746650A EP1642995A4 (en) | 2003-07-04 | 2004-06-30 | METHOD FOR CONTINUOUS VACUUM CARBURATION OF METAL CABLE, METAL STRIP, OR METAL PIPE, AND ASSOCIATED APPARATUS |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0039370A KR100506191B1 (ko) | 2002-07-08 | 2002-07-08 | 플래쉬 메모리 소자에서의 트림 비트 신호 생성 회로 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004039225A true JP2004039225A (ja) | 2004-02-05 |
JP4593089B2 JP4593089B2 (ja) | 2010-12-08 |
Family
ID=29997480
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003271035A Expired - Fee Related JP4593089B2 (ja) | 2002-07-08 | 2003-07-04 | フラッシュメモリ素子におけるトリムビット信号生成回路 |
Country Status (3)
Country | Link |
---|---|
US (1) | US6950339B2 (ja) |
JP (1) | JP4593089B2 (ja) |
KR (1) | KR100506191B1 (ja) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4642771B2 (ja) * | 2003-10-22 | 2011-03-02 | ネックス システムズ インコーポレイテッド | ワークピースを流体処理する方法及び装置 |
US7583547B2 (en) * | 2005-09-29 | 2009-09-01 | Hynix Semiconductor, Inc. | Over-driving circuit in semiconductor memory device |
US7423445B2 (en) * | 2006-07-17 | 2008-09-09 | Qimonda North America Corp. | Method and system for trimming voltage or current references |
TWI413634B (zh) * | 2006-07-19 | 2013-11-01 | Syngenta Participations Ag | 除草組成物及其使用方法 |
KR100805838B1 (ko) * | 2006-08-10 | 2008-02-21 | 삼성전자주식회사 | 엑스아이피 플래시 메모리 장치 및 그 프로그램 방법 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5575269A (en) * | 1978-11-29 | 1980-06-06 | Ibm | Continuity parameter regulator |
JPH05258595A (ja) * | 1991-12-27 | 1993-10-08 | Nec Corp | 半導体記憶装置 |
JPH10214496A (ja) * | 1997-01-31 | 1998-08-11 | Hitachi Ltd | 半導体集積回路及びマイクロコンピュータ |
JPH1187662A (ja) * | 1997-09-08 | 1999-03-30 | Sony Corp | 不揮発性半導体記憶装置及びその書き込み方法 |
JPH11232895A (ja) * | 1998-02-18 | 1999-08-27 | Matsushita Electric Ind Co Ltd | 不揮発性メモリ |
JP2001057088A (ja) * | 1999-08-16 | 2001-02-27 | Fujitsu Ltd | Nand型不揮発性メモリ |
WO2001093275A1 (en) * | 2000-05-30 | 2001-12-06 | Hitachi,Ltd | Semiconductor device and mobile communication terminal |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5243239A (en) * | 1991-01-22 | 1993-09-07 | Information Storage Devices, Inc. | Integrated MOSFET resistance and oscillator frequency control and trim methods and apparatus |
US5671183A (en) * | 1994-12-29 | 1997-09-23 | Texas Instruments Incorporated | Method for programming permanent calibration information at final test without increasing pin count |
US5973956A (en) * | 1995-07-31 | 1999-10-26 | Information Storage Devices, Inc. | Non-volatile electrically alterable semiconductor memory for analog and digital storage |
US5933370A (en) * | 1998-01-09 | 1999-08-03 | Information Storage Devices, Inc. | Trimbit circuit for flash memory |
JP2000048591A (ja) * | 1998-07-29 | 2000-02-18 | Hitachi Ltd | 半導体集積回路装置 |
KR20000020229A (ko) * | 1998-09-18 | 2000-04-15 | 김영환 | 메모리장치의 기준전압 트리밍 방법 |
KR100287185B1 (ko) * | 1999-03-22 | 2001-04-16 | 윤종용 | 퓨즈의 절단 없이도 퓨즈 절단의 효과를 얻어 반복해서 전압 레벨을 트리밍 할 수 있는 전압 레벨 발생회로 및 이를 이용하여전압 레벨을 트리밍하는 방법 |
US6424211B1 (en) * | 2000-06-26 | 2002-07-23 | Microchip Technology Incorporated | Digital trimming of OP AMP offset voltage and quiescent current using non-volatile memory |
-
2002
- 2002-07-08 KR KR10-2002-0039370A patent/KR100506191B1/ko not_active IP Right Cessation
-
2003
- 2003-06-17 US US10/462,717 patent/US6950339B2/en not_active Expired - Fee Related
- 2003-07-04 JP JP2003271035A patent/JP4593089B2/ja not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5575269A (en) * | 1978-11-29 | 1980-06-06 | Ibm | Continuity parameter regulator |
JPH05258595A (ja) * | 1991-12-27 | 1993-10-08 | Nec Corp | 半導体記憶装置 |
JPH10214496A (ja) * | 1997-01-31 | 1998-08-11 | Hitachi Ltd | 半導体集積回路及びマイクロコンピュータ |
JPH1187662A (ja) * | 1997-09-08 | 1999-03-30 | Sony Corp | 不揮発性半導体記憶装置及びその書き込み方法 |
JPH11232895A (ja) * | 1998-02-18 | 1999-08-27 | Matsushita Electric Ind Co Ltd | 不揮発性メモリ |
JP2001057088A (ja) * | 1999-08-16 | 2001-02-27 | Fujitsu Ltd | Nand型不揮発性メモリ |
WO2001093275A1 (en) * | 2000-05-30 | 2001-12-06 | Hitachi,Ltd | Semiconductor device and mobile communication terminal |
Also Published As
Publication number | Publication date |
---|---|
US20040004874A1 (en) | 2004-01-08 |
KR100506191B1 (ko) | 2005-08-04 |
US6950339B2 (en) | 2005-09-27 |
JP4593089B2 (ja) | 2010-12-08 |
KR20040005079A (ko) | 2004-01-16 |
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