JP2003031650A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JP2003031650A
JP2003031650A JP2001213689A JP2001213689A JP2003031650A JP 2003031650 A JP2003031650 A JP 2003031650A JP 2001213689 A JP2001213689 A JP 2001213689A JP 2001213689 A JP2001213689 A JP 2001213689A JP 2003031650 A JP2003031650 A JP 2003031650A
Authority
JP
Japan
Prior art keywords
silicon oxide
oxide film
groove
film
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
JP2001213689A
Other languages
English (en)
Japanese (ja)
Other versions
JP2003031650A5 (https=
Inventor
Yukio Nishiyama
山 幸 男 西
Hirotaka Ogiwara
原 博 隆 荻
Renpei Nakada
田 錬 平 中
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2001213689A priority Critical patent/JP2003031650A/ja
Priority to US10/193,143 priority patent/US7052971B2/en
Publication of JP2003031650A publication Critical patent/JP2003031650A/ja
Publication of JP2003031650A5 publication Critical patent/JP2003031650A5/ja
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/014—Manufacture or treatment of isolation regions comprising dielectric materials using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/17—Isolation regions comprising dielectric materials formed using trench refilling with dielectric materials, e.g. shallow trench isolations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6687—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and nitrogen
    • H10P14/6689—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and nitrogen the compound being a silazane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/06—Planarisation of inorganic insulating materials
    • H10P95/062—Planarisation of inorganic insulating materials involving a dielectric removal step
    • H10P95/064—Planarisation of inorganic insulating materials involving a dielectric removal step the removal being chemical etching

Landscapes

  • Element Separation (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
JP2001213689A 2001-07-13 2001-07-13 半導体装置の製造方法 Abandoned JP2003031650A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001213689A JP2003031650A (ja) 2001-07-13 2001-07-13 半導体装置の製造方法
US10/193,143 US7052971B2 (en) 2001-07-13 2002-07-12 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001213689A JP2003031650A (ja) 2001-07-13 2001-07-13 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
JP2003031650A true JP2003031650A (ja) 2003-01-31
JP2003031650A5 JP2003031650A5 (https=) 2005-07-07

Family

ID=19048626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001213689A Abandoned JP2003031650A (ja) 2001-07-13 2001-07-13 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US7052971B2 (https=)
JP (1) JP2003031650A (https=)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004342960A (ja) * 2003-05-19 2004-12-02 Sony Corp 半導体装置および半導体装置の製造方法
US7052971B2 (en) * 2001-07-13 2006-05-30 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device
US7105397B2 (en) 2003-11-28 2006-09-12 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
JP2006339446A (ja) * 2005-06-02 2006-12-14 Toshiba Corp 半導体装置およびその製造方法
US7279769B2 (en) 2004-05-25 2007-10-09 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
KR100780617B1 (ko) * 2006-06-29 2007-11-29 주식회사 하이닉스반도체 반도체 소자의 제조방법
US7332409B2 (en) 2004-06-11 2008-02-19 Samsung Electronics Co., Ltd. Methods of forming trench isolation layers using high density plasma chemical vapor deposition
US7601588B2 (en) 2004-11-04 2009-10-13 Samsung Electronics Co., Ltd. Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same
US7682927B2 (en) 2005-03-25 2010-03-23 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
KR20100121437A (ko) 2009-05-08 2010-11-17 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치 및 그 제조 방법
US8080463B2 (en) 2009-01-23 2011-12-20 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and silicon oxide film forming method
US8329553B2 (en) 2009-06-08 2012-12-11 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device and NAND-type flash memory

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JP2004273519A (ja) * 2003-03-05 2004-09-30 Clariant (Japan) Kk トレンチ・アイソレーション構造の形成方法
US7214595B2 (en) * 2003-06-27 2007-05-08 Kabushiki Kaisha Toshiba Method of producing semiconductor devices
DE102004005804B4 (de) * 2004-02-06 2007-04-05 X-Fab Semiconductor Foundries Ag Verfahren zur Verfüllung von Isolationsgräben unter Nutzung von CMOS-Standardprozessen zur Realisierung dielektrisch isolierter Gebiete auf SOI Scheiben
US7112513B2 (en) * 2004-02-19 2006-09-26 Micron Technology, Inc. Sub-micron space liner and densification process
US7271464B2 (en) * 2004-08-24 2007-09-18 Micron Technology, Inc. Liner for shallow trench isolation
US7809537B2 (en) * 2004-10-15 2010-10-05 Saudi Arabian Oil Company Generalized well management in parallel reservoir simulation
US7271463B2 (en) * 2004-12-10 2007-09-18 Micron Technology, Inc. Trench insulation structures including an oxide liner that is thinner along the walls of the trench than along the base
JP2006196843A (ja) * 2005-01-17 2006-07-27 Toshiba Corp 半導体装置およびその製造方法
US7596480B2 (en) * 2005-04-14 2009-09-29 Saudi Arabian Oil Company Solution method and apparatus for large-scale simulation of layered formations
JP4509868B2 (ja) * 2005-06-07 2010-07-21 株式会社東芝 半導体装置の製造方法
JP4984558B2 (ja) * 2006-02-08 2012-07-25 富士通セミコンダクター株式会社 半導体装置の製造方法
EP1840940B8 (de) * 2006-03-28 2014-11-26 Thallner, Erich, Dipl.-Ing. Vorrichtung und Verfahren zum Beschichten eines mikro- und/oder nanostrukturierten Struktursubstrats
JP2007335807A (ja) * 2006-06-19 2007-12-27 Toshiba Corp 半導体装置の製造方法
JP2008091368A (ja) * 2006-09-29 2008-04-17 Toshiba Corp 半導体装置及びその製造方法
JP2008091614A (ja) * 2006-10-02 2008-04-17 Toshiba Corp 半導体装置およびその製造方法
KR100757335B1 (ko) * 2006-10-18 2007-09-11 삼성전자주식회사 불휘발성 메모리 장치 및 이를 제조하는 방법
US20080227267A1 (en) * 2007-03-14 2008-09-18 Theodorus Gerardus Maria Oosterlaken Stop mechanism for trench reshaping process
US7892942B2 (en) * 2007-07-09 2011-02-22 Micron Technology Inc. Methods of forming semiconductor constructions, and methods of forming isolation regions
JP2009076637A (ja) * 2007-09-20 2009-04-09 Toshiba Corp 不揮発性半導体記憶装置およびその製造方法
US8101497B2 (en) 2008-09-11 2012-01-24 Micron Technology, Inc. Self-aligned trench formation
KR101795658B1 (ko) * 2009-01-31 2017-11-08 어플라이드 머티어리얼스, 인코포레이티드 에칭을 위한 방법 및 장치
JP5670777B2 (ja) * 2011-02-10 2015-02-18 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
CN103794543B (zh) * 2012-10-31 2018-07-10 中芯国际集成电路制造(上海)有限公司 隔离结构及其形成方法
CN104752320B (zh) * 2013-12-27 2017-12-29 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN108110008B (zh) * 2016-11-25 2020-07-28 旺宏电子股份有限公司 半导体元件及其制造方法与存储器的制造方法
CN107170708A (zh) * 2017-05-08 2017-09-15 上海华力微电子有限公司 利于填充的通孔制作方法
KR102757527B1 (ko) * 2018-09-05 2025-01-22 삼성전자주식회사 갭필막, 그 형성 방법, 및 그 형성 방법에 의해 제조된 반도체 소자

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JPS5958837A (ja) 1982-09-29 1984-04-04 Fujitsu Ltd 半導体装置の製造方法
JPS59225543A (ja) 1983-06-06 1984-12-18 Mitsubishi Electric Corp 素子間分離領域の形成方法
US6448150B1 (en) * 1998-01-20 2002-09-10 Nanya Technology Corporation Method for forming shallow trench isolation in the integrated circuit
US6395150B1 (en) * 1998-04-01 2002-05-28 Novellus Systems, Inc. Very high aspect ratio gapfill using HDP
JP2000114362A (ja) 1998-10-02 2000-04-21 Nec Corp 半導体装置の製造方法
US6024106A (en) * 1998-11-19 2000-02-15 United Microelectronics Corp. Post-CMP wafer clean process
JP2000183150A (ja) 1998-12-11 2000-06-30 Matsushita Electronics Industry Corp 半導体装置の製造方法
JP2000294627A (ja) 1999-04-09 2000-10-20 Seiko Epson Corp 半導体装置の製造方法
JP2000332099A (ja) 1999-05-21 2000-11-30 Matsushita Electronics Industry Corp 半導体装置およびその製造方法
US6380047B1 (en) * 1999-08-10 2002-04-30 Advanced Micro Devices, Inc. Shallow trench isolation formation with two source/drain masks and simplified planarization mask
KR100297736B1 (ko) * 1999-08-13 2001-11-01 윤종용 트렌치 소자분리방법
JP2001135718A (ja) 1999-11-08 2001-05-18 Nec Corp トレンチ分離構造の作製方法
US6391781B1 (en) * 2000-01-06 2002-05-21 Oki Electric Industry Co., Ltd. Method of making a semiconductor device
JP2001244327A (ja) 2000-03-02 2001-09-07 Sanyo Electric Co Ltd 半導体装置の製造方法
JP3492279B2 (ja) * 2000-03-21 2004-02-03 Ｎｅｃエレクトロニクス株式会社 素子分離領域の形成方法
US6335288B1 (en) * 2000-08-24 2002-01-01 Applied Materials, Inc. Gas chemistry cycling to achieve high aspect ratio gapfill with HDP-CVD
US6479405B2 (en) * 2000-10-12 2002-11-12 Samsung Electronics Co., Ltd. Method of forming silicon oxide layer in semiconductor manufacturing process using spin-on glass composition and isolation method using the same method
US6740601B2 (en) * 2001-05-11 2004-05-25 Applied Materials Inc. HDP-CVD deposition process for filling high aspect ratio gaps
JP2003031650A (ja) * 2001-07-13 2003-01-31 Toshiba Corp 半導体装置の製造方法
US20030162363A1 (en) * 2002-02-22 2003-08-28 Hua Ji HDP CVD process for void-free gap fill of a high aspect ratio trench
US7141138B2 (en) * 2002-09-13 2006-11-28 Applied Materials, Inc. Gas delivery system for semiconductor processing
JP2004311487A (ja) * 2003-04-02 2004-11-04 Hitachi Ltd 半導体装置の製造方法

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7052971B2 (en) * 2001-07-13 2006-05-30 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device
JP2004342960A (ja) * 2003-05-19 2004-12-02 Sony Corp 半導体装置および半導体装置の製造方法
US7105397B2 (en) 2003-11-28 2006-09-12 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US7416987B2 (en) 2003-11-28 2008-08-26 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US7279769B2 (en) 2004-05-25 2007-10-09 Renesas Technology Corp. Semiconductor device and manufacturing method thereof
US7332409B2 (en) 2004-06-11 2008-02-19 Samsung Electronics Co., Ltd. Methods of forming trench isolation layers using high density plasma chemical vapor deposition
US7601588B2 (en) 2004-11-04 2009-10-13 Samsung Electronics Co., Ltd. Method of forming a trench isolation layer and method of manufacturing a non-volatile memory device using the same
US7682927B2 (en) 2005-03-25 2010-03-23 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor device
JP2006339446A (ja) * 2005-06-02 2006-12-14 Toshiba Corp 半導体装置およびその製造方法
US8106475B2 (en) 2005-06-02 2012-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
KR100780617B1 (ko) * 2006-06-29 2007-11-29 주식회사 하이닉스반도체 반도체 소자의 제조방법
US8080463B2 (en) 2009-01-23 2011-12-20 Kabushiki Kaisha Toshiba Semiconductor device manufacturing method and silicon oxide film forming method
KR20100121437A (ko) 2009-05-08 2010-11-17 르네사스 일렉트로닉스 가부시키가이샤 반도체 장치 및 그 제조 방법
US8384187B2 (en) 2009-05-08 2013-02-26 Renesas Electronics Corporation Semiconductor device with shallow trench isolation
US9029237B2 (en) 2009-05-08 2015-05-12 Renesas Electronics Corporation Semiconductor device and method of manufacturing the same
US8329553B2 (en) 2009-06-08 2012-12-11 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor device and NAND-type flash memory

Also Published As

Publication number Publication date
US7052971B2 (en) 2006-05-30
US20030022522A1 (en) 2003-01-30

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