JP2002511188A - チップカードのための電子モジュール - Google Patents

チップカードのための電子モジュール

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Publication number
JP2002511188A
JP2002511188A JP54121098A JP54121098A JP2002511188A JP 2002511188 A JP2002511188 A JP 2002511188A JP 54121098 A JP54121098 A JP 54121098A JP 54121098 A JP54121098 A JP 54121098A JP 2002511188 A JP2002511188 A JP 2002511188A
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Japan
Prior art keywords
substrate
electronic module
contact
card
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP54121098A
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English (en)
Other versions
JP3869860B2 (ja
Inventor
ザフラニー，ミカエル
パトリス，フィリップ
Original Assignee
ジェムプリュス エス．セー．アー．
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Publication of JP2002511188A publication Critical patent/JP2002511188A/ja
Application granted granted Critical
Publication of JP3869860B2 publication Critical patent/JP3869860B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07743—External electrical contacts
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Abstract

(57)【要約】 本発明は、とくにカード型の電子デバイスに取り付けるための、接触トラック（４６；４８；５０）を備えた少なくとも一つの表面（４４）を有する基板（４０）と前記基板（４０）上に固定され、それぞれ基板の接触トラックに接続された出力固定電極（６０、６２）を含むマイクロ回路（５６）とから成る電子モジュールに関するものである。本発明は、出力固定電極と接触トラックの間の接続（６６、６８）が、基板の起伏に沿った接着導電性物質のビードによって構成されることを特徴とする。有利には、導電性物質は等方導電性接合剤である。

Description

【発明の詳細な説明】 チップカードのための電子モジュール 本発明は、とくにカード型の電子デバイスに取り付けるための、接触トラック を備えた少なくとも一つの面を含む基板と、前記基板上に固定され、基板の接触 トラックにそれぞれ接続された出力固定電極を含むマイクロ回路とを含む、電子 モジュールに関するものである。 カード型のかかるデバイスは、とくに、チップカードとも呼ばれるＩＣカード だけでなく、テレビ、ビデオデッキなどのための電子要素の基板も含んでいる。 チップカードは、カード本体とチップを含み、カード本体に組み込まれたモジ ュールで構成されている。 チップカードモジュールは、接触トラックを有するように一つの面上に、金属 被覆化された一般的にエポキシガラス製の基板と、基板のもう一方の面に接着さ れその外面に出力固定電極を含むチップで構成されている。接続井戸は、出力固 定電極を接触トラックに連結する接続線の通過のために基板を通って配置されて いる。 金やアルミニウムなどの不銹性金属製の接続線は、その保護のために、樹脂を 用いてそれらを後から封止（"glob top"）する必要のある、超音波または熱圧縮 によるはんだ付けなどの、各種技術を用いて溶接される。ときには、基板上に、 金属またはシリコン環などの、樹脂保持障壁をあらかじめ固定する必要がある。 樹脂の塊は制御し得ない仕方で据えられ、それが重合したときに、高さがチッ プカードの仕様を越えるような大きな厚みの滴を形成する。したがって、モジュ ールの厚みを要求値まで減らすためにフライス削り作業を実施する必要がある。 このフライス削り作業はモジュールを損傷する可能性があり、製造過程に生じる 不良品の主な原因になっている。 チップカード本体に、相当な高さのモジュールを収納できるよう比較的深くな ければならない、モジュール収容用凹部が作られる。その結果、凹部の領域での カード本体の厚みが薄くなり、その結果、チップカードが曲げ応力を受けたとき に、カード本体に大きな変形が生じ、それによってカードの信頼性と寿命が制限 される。 くわえて、この樹脂滴の重合によってモジュールの反り返り現象が引き起こさ れる。 この反り返りがチップカード読取器の劣化を招く恐れがある。 本発明の基本的課題は、上記の欠点を解消するように高さを減じた電子モジュ ールを提供することにある。 本発明による電子モジュールは、出力固定電極と接触トラック間の接続が基板 の起伏に沿った接着導電性物質のビードによって構成される点がとくに注目され る。 これらの接続は保護のための封止が不要で、そのためモジュールの高さを大幅 に減らすことができる。その結果、製造が単純化され、とくに、フライス削り作 業が省略され、それによって製造過程における不良率が大幅に下がる。 有利には、導電性物質は等方導電性接着剤である。 またシルクスクリーン印刷で付着させた金属を用いることもできる。 基板が接続井戸を含んでいる場合、それらは導電性物質で充填さている。 基板は、接触トラックを備えた２つの面を含むことが可能で、接続は接続井戸 を用いることなしに２つの面で直接実現される。 有利には、基板の面の一つは活性化可能な接着性被膜で覆われる。 これがマイクロ回路の追加の保護になり、カード本体のモジュールの固定作業 を単純化することができる。 マイクロ回路の出力固定電極は接触抵抗を減らすように接続バンプを備えるこ とができる。 本発明はまた、ビードが粘着性のある導電性物質の付着によって実現されるこ とを特徴とする、電子モジュールの製造方法も対象とする。 注入器または類似物の手段によるこの付着技術は実施が迅速で容易である。 本発明はさらに、上記のタイプの少なくとも一つの電子モジュールを含むこと を特徴とするチップカードも対象とする。 本発明のその他の特徴と利点は以下の詳細な説明を理解するために付属の図面 を参照し、その説明を読むことによって明らかになるだろう： −図１は、既知のタイプの電子モジュールの、横断面図である： −図２は、本発明と同一の電子モジュールの図である： −図３は、基板が、接触トラックを備えた２つの面を含むモジュールの実施態 様の平面図である： 図１は既知のタイプの電子モジュールの図である。 それは、例えばエポキシガラス製の基板１０を含む。その面の一つ１２は金属 被覆化によって実現された接触トラック１４を含む。他の面１６は、出力固定電 極２２を含むマイクロ回路２０の下面を、その空いた上面に固定するのに役立つ 接着剤層１８を備えている。 出力固定電極２２と接触トラック１４間の接続は、基板１０で実現された接続 井戸２６を介して、それぞれ通過する金属線２４のはんだ付けによって実現され る。線２４のはんだ付け作業の後、それらは、シリコン製の周縁環３０によって 保持される滴２８を形成する重合可能な樹脂によって封止される。 この滴２８は制御されない仕方で付着され、相当の厚みがあり、モジュールの 高さを著しく増すので、点線３２で図解した如く、フライス削りなどの、加工作 業によってその上部を平坦化する必要がある。 先に述べた如く、この滴２８が存在するためにモジュールを収納する凹部の領 域でチップカートの機械的強度が低下し、その結果、この領域でのカードの機械 的強度が不足し、さらにカードがこの領域で反り返る恐れがある。 図２は、本発明と同一の電子モジュールの図である。基板４０は接続井戸４２ を含んでいる。基板４０の内面４４は金属被覆化され、接触トラック４６、４８ と５０を含んでいる。基板４０の上面５２は、図示されていない接触バンプ （"bumps"）を備えることができる出力固定電極６０と６２を、その上面５８に 有するチップ５６の固定に役立つ接着剤の層５４を有する。絶縁接合剤の被覆６ ４がチップ５６の周縁、チップの近傍の基板の面５２と接続井戸４２内に塗布さ れる。 本発明によれば、出力固定電極６０と６２と接触トラック４６と５０間の接続 ６６と６８は基板の起伏に適合する、より具体的には、接着被覆６４と接触し、 その両端が出力固定電極および組み合わされた接触トラックと接触している接着 導電性物質のビードによって構成される。この物質は粘着状態で塗布される。 この物質、例えば、等方導電性接着剤の塗布は、「ディスペンス」と呼ばれる 付着技術によって実現され、それによって、液状または低粘度の物質を流量と開 口が制御された注入器または類似物の手段によって付着させる。 このディスペンス作業は例えば、米国のCamelot Systems Inc.によってＣＡＭ ／ＡＬＯＴの名称で市販され、電子回路ラインの実現に用いられている設備によ って実現される。注入器の移動と開口は情報処理プログラムによって制御される 。 これらの接続はシルクスクリーン印刷で付着させた金属を用いて実現すること もできる。 電気接触向上のために、出力固定電極は接触ボスを含むことが可能で、導電性 物質のビードの端部の接触は後者によって行われる。 本発明は基板が接触トラックを含む金属被覆化した２つの面を含む場合にも適 用できる。 これはモジュールの上面の一部である図３に示され、出力固定電極７２、７４ 、７６、７８および８０を備えたチップ７０が見える。出力固定電極７２、７４ と７６は基板の下面の接触トラックに接続され、固定電極７８と８０は、おなじ く各接着導電性物質のビード８６、８８によって基板の上面に配置された、トラ ック８２、８４にそれぞれ接続されている。 本発明による電子モジュールは、一方では、チップの保護性を向上し、他方で は、カード本体の凹部へのモジュールの固定作業を簡易化するために、例えば、 加熱または紫外線によって活性化できる接着フィルムによって覆うことができる 。 本発明による直接接続の実現は、ビデオデッキまたは家電製品の制御カードな どのカードの形をしたいっさいの電子デバイスの製造に適用することができる。 以上でわかるように、本発明は接続の封止をなくし、その結果、モジュールの 厚みを減少することを可能にする。 他方で、導電性物質として用いた樹脂はきわめて柔軟であり、それによってモ ジュールの信頼性が向上する。 接続の封止に関連する作業、すなわちシリコン環などの保持障壁の設置、封止 樹脂の付着、樹脂滴の加工などは不要になる。その結果製造が単純化され、製造 コストが下がる。 本発明はモジュール領域でもっと大きなカード本体の厚みを有すること、つま り、カードの機械的強度を増すことを可能にする。 本発明により、マイクロ回路平面内のモジュールの寸法を減らすことができ、 それによってモジュールの隣接する２つのラインでモジュールを大量生産するこ とができる。 最後に、本発明によって反り返り現象をなくし、その結果、読取器の劣化を防 止することができる。

Claims (1)

  1. 【特許請求の範囲】 １．とくにカード型の電子デバイス内に取り付けるための、接触トラック（１ ４；４６；４８；５０）を備えた少なくとも一つの面（１２；４４）を含む基板 （１０；４０；１０８）と、前記基板（１０；４０；１０８）上に固定され、基 板の接触トラックにそれぞれ接続された出力固定電極（２２；６０、６２；７２ 、７４、７６、７８、８０）を含むマイクロ回路（２０；５６；７０；９８）と から成り、出力固定電極と接触トラック間の接続（６６、６８；８６、８８）が 基板の起伏に沿った接着導電性物質のビードによって構成されることを特徴とす る電子モジュール。 ２．ビードが粘性のある導電性物質の付着によって実現されることを特徴とす る、請求項１に記載の電子モジュールの製造方法。 ３．導電性物質が等方導電性接着剤であることを特徴とする、請求項１に記載 の電子モジュール。 ４．基板が接触トラックを備えた２つの面を含んでいることを特徴とする、請 求項１から３のいずれか一つに記載の電子モジュール。 ５．基板の面の一つが活性化可能な接着フィルムで覆われていることを特徴と する、請求項１から４のいずれか一つに記載の電子モジュール。 ６．マイクロ回路の出力固定電極が接続バンプを含むことを特徴とする、請求 項１から５のいずれか一つに記載の電子モジュール。 ７．請求項１から６のいずれか一つに記載の少なくとも一つの電子モジュール を含むことを特徴とするチップカード。
JP54121098A 1997-03-27 1998-03-09 チップカードのための電子モジュール Expired - Fee Related JP3869860B2 (ja)

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PCT/FR1998/000500 WO1998044451A1 (fr) 1997-03-27 1998-03-09 Module electronique pour carte a puce

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FR2761498B1 (fr) * 1997-03-27 1999-06-18 Gemplus Card Int Module electronique et son procede de fabrication et carte a puce comportant un tel module
FR2785072B1 (fr) * 1998-10-23 2001-01-19 St Microelectronics Sa Circuit electronique autocollant
FR2797075B1 (fr) * 1999-07-26 2001-10-12 Gemplus Card Int Procede de fabrication de dispositif portable a circuits integres, de type carte a puce de format reduit par rapport au format standard
FR2797995B1 (fr) * 1999-08-25 2002-03-22 Gemplus Card Int Procede de protection de puces de circuit integre par depot de couche mince isolante
FR2797996B1 (fr) * 1999-08-25 2003-10-03 Gemplus Card Int Procede de protection de puces de circuit integre par depot de couche mince isolante
FR2799306B1 (fr) * 1999-10-04 2003-09-19 Gemplus Card Int Procede d'isolation de puce de circuit integre par depot de matiere sur la face active
FR2800198B1 (fr) * 1999-10-26 2002-03-29 Gemplus Card Int Procede de protection de puces de circuit integre par aspiration sous vide
FR2808920B1 (fr) * 2000-05-10 2003-10-03 Gemplus Card Int Procede de protection de puces de circuit integre
FR2818801B1 (fr) * 2000-12-21 2003-04-04 Gemplus Card Int Interconnexion par organe d'isolation decoupe et cordon de conduction
FR2818800B1 (fr) * 2000-12-21 2003-04-04 Gemplus Card Int Interconnexion par organe deformable pour dispositif electronique
FR2823011B1 (fr) * 2001-03-30 2004-11-19 Gemplus Card Int Connexion par depot de cordon conductrice sur zone de raccordement delimitee par masque isolant
FR2845805B1 (fr) * 2002-10-10 2005-06-03 Gemplus Card Int Adhesif d'encartage formant navette
FR2847365B1 (fr) * 2002-11-15 2005-03-11 Gemplus Card Int Connexion/raccordement simultane par un percage d'adhesif d'encartage
US7243421B2 (en) * 2003-10-29 2007-07-17 Conductive Inkjet Technology Limited Electrical connection of components
WO2007042071A1 (de) * 2005-10-10 2007-04-19 Alphasem Ag Baugruppe mit wenigstens zwei in elektrisch leitender wirkverbindung stehenden komponenten und verfahren zum herstellen der baugruppe
DE102006056361B4 (de) * 2006-11-29 2012-08-16 Infineon Technologies Ag Modul mit polymerhaltigem elektrischen Verbindungselement und Verfahren
DE102008019571A1 (de) 2008-04-18 2009-10-22 Giesecke & Devrient Gmbh Chipkarte und Verfahren zu deren Herstellung
TWM425346U (en) * 2011-05-20 2012-03-21 Mxtran Inc Integrated circuit film for smart card and mobile communication device
US8991711B2 (en) * 2012-07-19 2015-03-31 Infineon Technologies Ag Chip card module
MY184608A (en) * 2013-12-10 2021-04-07 Carsem M Sdn Bhd Pre-molded integrated circuit packages
DE102014105861B4 (de) * 2014-04-25 2015-11-05 Infineon Technologies Ag Sensorvorrichtung und Verfahren zum Herstellen einer Sensorvorrichtung

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3338597A1 (de) * 1983-10-24 1985-05-02 GAO Gesellschaft für Automation und Organisation mbH, 8000 München Datentraeger mit integriertem schaltkreis und verfahren zur herstellung desselben
US4999136A (en) * 1988-08-23 1991-03-12 Westinghouse Electric Corp. Ultraviolet curable conductive resin
US5255430A (en) * 1992-10-08 1993-10-26 Atmel Corporation Method of assembling a module for a smart card
DE4325458A1 (de) * 1993-07-29 1995-02-09 Orga Bond Technik Gmbh Trägerelement für einen IC-Baustein
US5689136A (en) * 1993-08-04 1997-11-18 Hitachi, Ltd. Semiconductor device and fabrication method
DE9315652U1 (de) * 1993-10-15 1993-12-23 Nordson Corp Auftragskopf zum Aufbringen von Klebstoff auf ein Substrat, insbesondere für eine Verklebung eines Chips mit einer Karte
US5423889A (en) * 1994-06-24 1995-06-13 Harris Corporation Process for manufacturing a multi-port adhesive dispensing tool
JPH0839974A (ja) * 1994-07-27 1996-02-13 Dainippon Printing Co Ltd Ｉｃカード用ｉｃモジュールとその製造方法、及びｉｃカード
DE4441052A1 (de) * 1994-11-18 1996-05-23 Orga Kartensysteme Gmbh Trägerelement für einen IC-Baustein zum Einsatz in Chipkarten
DE69635397T2 (de) * 1995-03-24 2006-05-24 Shinko Electric Industries Co., Ltd. Halbleitervorrichtung mit Chipabmessungen und Herstellungsverfahren
JPH08310172A (ja) * 1995-05-23 1996-11-26 Hitachi Ltd 半導体装置
FR2761498B1 (fr) * 1997-03-27 1999-06-18 Gemplus Card Int Module electronique et son procede de fabrication et carte a puce comportant un tel module
US6107109A (en) * 1997-12-18 2000-08-22 Micron Technology, Inc. Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate

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FR2761498B1 (fr) 1999-06-18
US20020125329A1 (en) 2002-09-12
EP0970437A1 (fr) 2000-01-12
JP3869860B2 (ja) 2007-01-17
AU720691B2 (en) 2000-06-08
AU6922598A (en) 1998-10-22
HK1028833A1 (en) 2001-03-02
CN1183486C (zh) 2005-01-05
CN1257599A (zh) 2000-06-21
DE69832104T2 (de) 2006-11-23
DE69832104D1 (de) 2005-12-01
FR2761498A1 (fr) 1998-10-02
US6769619B2 (en) 2004-08-03
BR9808062A (pt) 2000-03-08
WO1998044451A1 (fr) 1998-10-08
EP1168240A2 (fr) 2002-01-02
EP1168240B1 (fr) 2005-10-26
EP1168240A3 (fr) 2002-01-30
RU2200975C2 (ru) 2003-03-20
CA2283692A1 (fr) 1998-10-08
US6435414B1 (en) 2002-08-20

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