JP2002508594A - メモリセル装置及びその製造方法 - Google Patents

メモリセル装置及びその製造方法

Info

Publication number
JP2002508594A
JP2002508594A JP2000538387A JP2000538387A JP2002508594A JP 2002508594 A JP2002508594 A JP 2002508594A JP 2000538387 A JP2000538387 A JP 2000538387A JP 2000538387 A JP2000538387 A JP 2000538387A JP 2002508594 A JP2002508594 A JP 2002508594A
Authority
JP
Japan
Prior art keywords
memory cell
memory cells
cell device
semiconductor substrate
bit lines
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2000538387A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002508594A5 (enExample
Inventor
ライジンガー、ハンス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of JP2002508594A publication Critical patent/JP2002508594A/ja
Publication of JP2002508594A5 publication Critical patent/JP2002508594A5/ja
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/18Bit line organisation; Bit line lay-out
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Landscapes

  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
JP2000538387A 1998-03-24 1999-03-17 メモリセル装置及びその製造方法 Pending JP2002508594A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19812948 1998-03-24
DE19812948.3 1998-03-24
PCT/DE1999/000762 WO1999049516A1 (de) 1998-03-24 1999-03-17 Speicherzellenanordnung und verfahren zu ihrer herstellung

Publications (2)

Publication Number Publication Date
JP2002508594A true JP2002508594A (ja) 2002-03-19
JP2002508594A5 JP2002508594A5 (enExample) 2009-03-26

Family

ID=7862152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000538387A Pending JP2002508594A (ja) 1998-03-24 1999-03-17 メモリセル装置及びその製造方法

Country Status (7)

Country Link
US (2) US6365944B1 (enExample)
EP (1) EP1068644B1 (enExample)
JP (1) JP2002508594A (enExample)
KR (1) KR100623144B1 (enExample)
CN (1) CN1165999C (enExample)
TW (1) TW432700B (enExample)
WO (1) WO1999049516A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7749840B2 (en) 2006-06-09 2010-07-06 Samsung Electronics Co., Ltd. Methods of forming a semiconductor device including buried bit line

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1080499A1 (en) * 1999-03-09 2001-03-07 Koninklijke Philips Electronics N.V. Semiconductor device comprising a non-volatile memory
JP4730999B2 (ja) * 2000-03-10 2011-07-20 スパンション エルエルシー 不揮発性メモリの製造方法
DE10051483A1 (de) * 2000-10-17 2002-05-02 Infineon Technologies Ag Nichtflüchtige Halbleiterspeicherzellenanordnung und Verfahren zu deren Herstellung
US6580120B2 (en) * 2001-06-07 2003-06-17 Interuniversitair Microelektronica Centrum (Imec Vzw) Two bit non-volatile electrically erasable and programmable memory structure, a process for producing said memory structure and methods for programming, reading and erasing said memory structure
US6630384B1 (en) * 2001-10-05 2003-10-07 Advanced Micro Devices, Inc. Method of fabricating double densed core gates in sonos flash memory
JP3967193B2 (ja) * 2002-05-21 2007-08-29 スパンション エルエルシー 不揮発性半導体記憶装置及びその製造方法
US7423310B2 (en) * 2004-09-29 2008-09-09 Infineon Technologies Ag Charge-trapping memory cell and charge-trapping memory device
US7804126B2 (en) 2005-07-18 2010-09-28 Saifun Semiconductors Ltd. Dense non-volatile memory array and method of fabrication
US8441063B2 (en) * 2010-12-30 2013-05-14 Spansion Llc Memory with extended charge trapping layer

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4651184A (en) * 1984-08-31 1987-03-17 Texas Instruments Incorporated Dram cell and array
JP2596198B2 (ja) 1990-08-30 1997-04-02 日本電気株式会社 Mos型読み出し専用半導体記憶装置
JPH05102436A (ja) * 1991-10-09 1993-04-23 Ricoh Co Ltd 半導体メモリ装置とその製造方法
US5278438A (en) 1991-12-19 1994-01-11 North American Philips Corporation Electrically erasable and programmable read-only memory with source and drain regions along sidewalls of a trench structure
DE19510042C2 (de) 1995-03-20 1997-01-23 Siemens Ag Festwert-Speicherzellenanordnung und Verfahren zu deren Herstellung
DE19514834C1 (de) * 1995-04-21 1997-01-09 Siemens Ag Festwertspeicherzellenanordnung und Verfahren zu deren Herstellung
KR0179807B1 (ko) * 1995-12-30 1999-03-20 문정환 반도체 기억소자 제조방법
KR100215840B1 (ko) * 1996-02-28 1999-08-16 구본준 반도체 메모리셀 구조 및 제조방법
US6118147A (en) * 1998-07-07 2000-09-12 Advanced Micro Devices, Inc. Double density non-volatile memory cells
US6207493B1 (en) * 1998-08-19 2001-03-27 International Business Machines Corporation Formation of out-diffused bitline by laser anneal

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7749840B2 (en) 2006-06-09 2010-07-06 Samsung Electronics Co., Ltd. Methods of forming a semiconductor device including buried bit line
US7846796B2 (en) 2006-06-09 2010-12-07 Samsung Electronics Co., Ltd. Semiconductor devices including buried bit lines

Also Published As

Publication number Publication date
KR20010042141A (ko) 2001-05-25
WO1999049516A1 (de) 1999-09-30
US6365944B1 (en) 2002-04-02
KR100623144B1 (ko) 2006-09-12
TW432700B (en) 2001-05-01
EP1068644A1 (de) 2001-01-17
CN1165999C (zh) 2004-09-08
CN1294759A (zh) 2001-05-09
US20020055247A1 (en) 2002-05-09
US6534362B2 (en) 2003-03-18
EP1068644B1 (de) 2015-07-08

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