JP2002343086A5 - - Google Patents

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Publication number
JP2002343086A5
JP2002343086A5 JP2002123589A JP2002123589A JP2002343086A5 JP 2002343086 A5 JP2002343086 A5 JP 2002343086A5 JP 2002123589 A JP2002123589 A JP 2002123589A JP 2002123589 A JP2002123589 A JP 2002123589A JP 2002343086 A5 JP2002343086 A5 JP 2002343086A5
Authority
JP
Japan
Prior art keywords
row
array
cells
asserting
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002123589A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002343086A (ja
Filing date
Publication date
Priority claimed from US09/845,387 external-priority patent/US6772277B2/en
Application filed filed Critical
Publication of JP2002343086A publication Critical patent/JP2002343086A/ja
Publication of JP2002343086A5 publication Critical patent/JP2002343086A5/ja
Pending legal-status Critical Current

Links

JP2002123589A 2001-04-30 2002-04-25 列クリアを用いてｒａｍに書き込む方法 Pending JP2002343086A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/845,387 US6772277B2 (en) 2001-04-30 2001-04-30 Method of writing to a memory array using clear enable and column clear signals
US09/845387 2001-04-30

Publications (2)

Publication Number Publication Date
JP2002343086A JP2002343086A (ja) 2002-11-29
JP2002343086A5 true JP2002343086A5 (enExample) 2005-09-29

Family

ID=25295121

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002123589A Pending JP2002343086A (ja) 2001-04-30 2002-04-25 列クリアを用いてｒａｍに書き込む方法

Country Status (5)

Country Link
US (1) US6772277B2 (enExample)
JP (1) JP2002343086A (enExample)
DE (1) DE10217290B4 (enExample)
FR (1) FR2828758B1 (enExample)
GB (1) GB2377797B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070014137A1 (en) * 2005-07-18 2007-01-18 Mellinger Todd W Banked cache with multiplexer
US7200020B2 (en) * 2005-08-30 2007-04-03 Freescale Semiconductor, Inc. Storage element with clear operation and method thereof
US7458040B1 (en) * 2005-09-01 2008-11-25 Synopsys, Inc. Resettable memory apparatuses and design
US20090144504A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US20090144507A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US8108609B2 (en) * 2007-12-04 2012-01-31 International Business Machines Corporation Structure for implementing dynamic refresh protocols for DRAM based cache
US8024513B2 (en) * 2007-12-04 2011-09-20 International Business Machines Corporation Method and system for implementing dynamic refresh protocols for DRAM based cache
US9646177B2 (en) * 2011-04-29 2017-05-09 Altera Corporation Systems and methods for preventing data remanence in memory systems
US11238923B2 (en) 2019-10-18 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222489A (ja) * 1982-06-18 1983-12-24 Nec Corp 半導体記憶装置
JPH0734311B2 (ja) * 1986-01-21 1995-04-12 株式会社東芝 メモリセル
US4805149A (en) * 1986-08-28 1989-02-14 Advanced Micro Devices, Inc. Digital memory with reset/preset capabilities
US4789967A (en) * 1986-09-16 1988-12-06 Advanced Micro Devices, Inc. Random access memory device with block reset
US4858182A (en) * 1986-12-19 1989-08-15 Texas Instruments Incorporated High speed zero power reset circuit for CMOS memory cells
EP0594266B1 (en) * 1988-05-18 1997-08-20 STMicroelectronics, Inc. SRAM with flash clear for selectable I/Os
US4928266A (en) * 1988-05-26 1990-05-22 Visic, Inc. Static ram with high speed, low power reset
US4890263A (en) * 1988-05-31 1989-12-26 Dallas Semiconductor Corporation RAM with capability for rapid clearing of data from memory by simultaneously selecting all row lines
JPH0289288A (ja) * 1988-09-27 1990-03-29 Toshiba Corp 半導体メモリ
JPH02121190A (ja) * 1988-10-28 1990-05-09 Fujitsu Ltd スタティック・ランダム・アクセス・メモリ
DE69024921T2 (de) * 1989-11-24 1996-09-05 Nippon Electric Co Halbleiterspeicheranordnung mit rückstellbaren Speicherzellen
US5235543A (en) * 1989-12-29 1993-08-10 Intel Corporation Dual port static memory with one cycle read-modify-write
JPH04360095A (ja) 1991-06-06 1992-12-14 Nec Corp 半導体記憶回路
JPH0745077A (ja) * 1993-08-02 1995-02-14 Nec Corp 記憶装置
US5710742A (en) * 1995-05-12 1998-01-20 International Business Machines Corporation High density two port SRAM cell for low voltage CMOS applications
US5742557A (en) * 1996-06-20 1998-04-21 Northern Telecom Limited Multi-port random access memory
FR2760286B1 (fr) * 1997-02-28 1999-04-16 Sgs Thomson Microelectronics Procede d'effacement d'une memoire ram statique et memoire en circuit integre associe
US6128215A (en) 1997-08-19 2000-10-03 Altera Corporation Static random access memory circuits
US6014732A (en) * 1997-10-22 2000-01-11 Hewlett-Packard Company Cache memory with reduced access time
US6208565B1 (en) * 2000-02-18 2001-03-27 Hewlett-Packard Company Multi-ported register structure utilizing a pulse write mechanism
US6301186B1 (en) * 2001-04-30 2001-10-09 Hewlett-Packard Company RAM cell with column clear

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