GB2377797B - Method of writing to a RAM with column clear - Google Patents

Method of writing to a RAM with column clear

Info

Publication number
GB2377797B
GB2377797B GB0208887A GB0208887A GB2377797B GB 2377797 B GB2377797 B GB 2377797B GB 0208887 A GB0208887 A GB 0208887A GB 0208887 A GB0208887 A GB 0208887A GB 2377797 B GB2377797 B GB 2377797B
Authority
GB
United Kingdom
Prior art keywords
writing
ram
column clear
clear
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0208887A
Other languages
English (en)
Other versions
GB2377797A (en
GB0208887D0 (en
Inventor
Samuel D Naffziger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of GB0208887D0 publication Critical patent/GB0208887D0/en
Publication of GB2377797A publication Critical patent/GB2377797A/en
Application granted granted Critical
Publication of GB2377797B publication Critical patent/GB2377797B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
GB0208887A 2001-04-30 2002-04-18 Method of writing to a RAM with column clear Expired - Fee Related GB2377797B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/845,387 US6772277B2 (en) 2001-04-30 2001-04-30 Method of writing to a memory array using clear enable and column clear signals

Publications (3)

Publication Number Publication Date
GB0208887D0 GB0208887D0 (en) 2002-05-29
GB2377797A GB2377797A (en) 2003-01-22
GB2377797B true GB2377797B (en) 2005-06-22

Family

ID=25295121

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0208887A Expired - Fee Related GB2377797B (en) 2001-04-30 2002-04-18 Method of writing to a RAM with column clear

Country Status (5)

Country Link
US (1) US6772277B2 (enExample)
JP (1) JP2002343086A (enExample)
DE (1) DE10217290B4 (enExample)
FR (1) FR2828758B1 (enExample)
GB (1) GB2377797B (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070014137A1 (en) * 2005-07-18 2007-01-18 Mellinger Todd W Banked cache with multiplexer
US7200020B2 (en) * 2005-08-30 2007-04-03 Freescale Semiconductor, Inc. Storage element with clear operation and method thereof
US7458040B1 (en) * 2005-09-01 2008-11-25 Synopsys, Inc. Resettable memory apparatuses and design
US20090144504A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation STRUCTURE FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US8024513B2 (en) * 2007-12-04 2011-09-20 International Business Machines Corporation Method and system for implementing dynamic refresh protocols for DRAM based cache
US8108609B2 (en) * 2007-12-04 2012-01-31 International Business Machines Corporation Structure for implementing dynamic refresh protocols for DRAM based cache
US20090144507A1 (en) * 2007-12-04 2009-06-04 International Business Machines Corporation APPARATUS AND METHOD FOR IMPLEMENTING REFRESHLESS SINGLE TRANSISTOR CELL eDRAM FOR HIGH PERFORMANCE MEMORY APPLICATIONS
US9646177B2 (en) * 2011-04-29 2017-05-09 Altera Corporation Systems and methods for preventing data remanence in memory systems
US11238923B2 (en) 2019-10-18 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430101A2 (en) * 1989-11-24 1991-06-05 Nec Corporation Semiconductor memory device having resettable memory cells
EP0517260A1 (en) * 1991-06-06 1992-12-09 Nec Corporation Semiconductor memory circuit having bit clear and/or register initialize function
EP0898281A2 (en) * 1997-08-19 1999-02-24 Altera Corporation Static random access memory circuits

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58222489A (ja) * 1982-06-18 1983-12-24 Nec Corp 半導体記憶装置
JPH0734311B2 (ja) * 1986-01-21 1995-04-12 株式会社東芝 メモリセル
US4805149A (en) * 1986-08-28 1989-02-14 Advanced Micro Devices, Inc. Digital memory with reset/preset capabilities
US4789967A (en) * 1986-09-16 1988-12-06 Advanced Micro Devices, Inc. Random access memory device with block reset
US4858182A (en) * 1986-12-19 1989-08-15 Texas Instruments Incorporated High speed zero power reset circuit for CMOS memory cells
DE68928270T2 (de) * 1988-05-18 1998-01-15 Sgs Thomson Microelectronics SRAM mit Flash-Rücksetzung für auswählbare E/A-Leitungen
US4928266A (en) * 1988-05-26 1990-05-22 Visic, Inc. Static ram with high speed, low power reset
US4890263A (en) * 1988-05-31 1989-12-26 Dallas Semiconductor Corporation RAM with capability for rapid clearing of data from memory by simultaneously selecting all row lines
JPH0289288A (ja) * 1988-09-27 1990-03-29 Toshiba Corp 半導体メモリ
JPH02121190A (ja) * 1988-10-28 1990-05-09 Fujitsu Ltd スタティック・ランダム・アクセス・メモリ
US5235543A (en) * 1989-12-29 1993-08-10 Intel Corporation Dual port static memory with one cycle read-modify-write
JPH0745077A (ja) * 1993-08-02 1995-02-14 Nec Corp 記憶装置
US5710742A (en) * 1995-05-12 1998-01-20 International Business Machines Corporation High density two port SRAM cell for low voltage CMOS applications
US5742557A (en) * 1996-06-20 1998-04-21 Northern Telecom Limited Multi-port random access memory
FR2760286B1 (fr) * 1997-02-28 1999-04-16 Sgs Thomson Microelectronics Procede d'effacement d'une memoire ram statique et memoire en circuit integre associe
US6014732A (en) * 1997-10-22 2000-01-11 Hewlett-Packard Company Cache memory with reduced access time
US6208565B1 (en) * 2000-02-18 2001-03-27 Hewlett-Packard Company Multi-ported register structure utilizing a pulse write mechanism
US6301186B1 (en) * 2001-04-30 2001-10-09 Hewlett-Packard Company RAM cell with column clear

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0430101A2 (en) * 1989-11-24 1991-06-05 Nec Corporation Semiconductor memory device having resettable memory cells
EP0517260A1 (en) * 1991-06-06 1992-12-09 Nec Corporation Semiconductor memory circuit having bit clear and/or register initialize function
EP0898281A2 (en) * 1997-08-19 1999-02-24 Altera Corporation Static random access memory circuits

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM technical disclosures bulletin Vol. 25, No. 12 May 1983 (US) Chao, H.H. "array arrangement and layout of taper-isolated dynamic gain RAM cell" pages 6387 to 6390, especially 6390 *

Also Published As

Publication number Publication date
GB2377797A (en) 2003-01-22
DE10217290B4 (de) 2010-04-08
JP2002343086A (ja) 2002-11-29
GB0208887D0 (en) 2002-05-29
FR2828758B1 (fr) 2006-09-22
US6772277B2 (en) 2004-08-03
US20020161964A1 (en) 2002-10-31
DE10217290A1 (de) 2002-11-07
FR2828758A1 (fr) 2003-02-21

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20100418