JP2001509316A - 低減寸法集積回路の製造法 - Google Patents

低減寸法集積回路の製造法

Info

Publication number
JP2001509316A
JP2001509316A JP53316598A JP53316598A JP2001509316A JP 2001509316 A JP2001509316 A JP 2001509316A JP 53316598 A JP53316598 A JP 53316598A JP 53316598 A JP53316598 A JP 53316598A JP 2001509316 A JP2001509316 A JP 2001509316A
Authority
JP
Japan
Prior art keywords
silicon
predetermined
amorphous
irradiation
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP53316598A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001509316A5 (https=
Inventor
タルワー，ソミット
クラマー，カール−ジョセフ
バーマ，グアラフ
ウェイナー，カート
Original Assignee
ウルトラテック ステッパー インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ウルトラテック ステッパー インコーポレイテッド filed Critical ウルトラテック ステッパー インコーポレイテッド
Publication of JP2001509316A publication Critical patent/JP2001509316A/ja
Publication of JP2001509316A5 publication Critical patent/JP2001509316A5/ja
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/202—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials
    • H10P30/204—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping characterised by the semiconductor materials into Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
    • H10D62/149—Source or drain regions of field-effect devices
    • H10D62/151—Source or drain regions of field-effect devices of IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/017—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P30/00—Ion implantation into wafers, substrates or parts of devices
    • H10P30/20—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping
    • H10P30/208—Ion implantation into wafers, substrates or parts of devices into semiconductor materials, e.g. for doping of electrically inactive species
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/14—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase
    • H10P32/1408—Diffusion of dopants within, into or out of semiconductor bodies or layers within a single semiconductor body or layer in a solid phase; between different semiconductor bodies or layers, both in a solid phase from or through or into an external applied layer, e.g. photoresist or nitride layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P32/00—Diffusion of dopants within, into or out of wafers, substrates or parts of devices
    • H10P32/10—Diffusion of dopants within, into or out of semiconductor bodies or layers
    • H10P32/17—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material
    • H10P32/171—Diffusion of dopants within, into or out of semiconductor bodies or layers characterised by the semiconductor material being group IV material
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/061—Gettering-armorphous layers

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
JP53316598A 1997-01-31 1998-01-29 低減寸法集積回路の製造法 Ceased JP2001509316A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/792,107 1997-01-31
US08/792,107 US5908307A (en) 1997-01-31 1997-01-31 Fabrication method for reduced-dimension FET devices
PCT/US1998/001942 WO1998034268A2 (en) 1997-01-31 1998-01-29 Fabrication method for reduced-dimension integrated circuits

Publications (2)

Publication Number Publication Date
JP2001509316A true JP2001509316A (ja) 2001-07-10
JP2001509316A5 JP2001509316A5 (https=) 2005-10-06

Family

ID=25155818

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53316598A Ceased JP2001509316A (ja) 1997-01-31 1998-01-29 低減寸法集積回路の製造法

Country Status (6)

Country Link
US (1) US5908307A (https=)
EP (1) EP1012879B1 (https=)
JP (1) JP2001509316A (https=)
KR (1) KR100511765B1 (https=)
DE (1) DE69807718T2 (https=)
WO (1) WO1998034268A2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932185B2 (en) 2003-06-02 2011-04-26 Sumitomo Heavy Industries, Ltd. Process for fabricating semiconductor device

Families Citing this family (84)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6361951B1 (en) * 1995-06-27 2002-03-26 The University Of North Carolina At Chapel Hill Electrochemical detection of nucleic acid hybridization
IT1289524B1 (it) * 1996-12-24 1998-10-15 Sgs Thomson Microelectronics Cella di memoria per dispositivi di tipo eeprom e relativo processo di fabbricazione
US6037640A (en) * 1997-11-12 2000-03-14 International Business Machines Corporation Ultra-shallow semiconductor junction formation
US5956603A (en) * 1998-08-27 1999-09-21 Ultratech Stepper, Inc. Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits
US6355543B1 (en) * 1998-09-29 2002-03-12 Advanced Micro Devices, Inc. Laser annealing for forming shallow source/drain extension for MOS transistor
US6297115B1 (en) * 1998-11-06 2001-10-02 Advanced Micro Devices, Inc. Cmos processs with low thermal budget
US6184112B1 (en) * 1998-12-02 2001-02-06 Advanced Micro Devices, Inc. Method of forming a MOSFET transistor with a shallow abrupt retrograde dopant profile
US6265291B1 (en) 1999-01-04 2001-07-24 Advanced Micro Devices, Inc. Circuit fabrication method which optimizes source/drain contact resistance
US6771895B2 (en) * 1999-01-06 2004-08-03 Mattson Technology, Inc. Heating device for heating semiconductor wafers in thermal processing chambers
US6395624B1 (en) * 1999-02-22 2002-05-28 International Business Machines Corporation Method for forming implants in semiconductor fabrication
US6521501B1 (en) * 1999-05-11 2003-02-18 Advanced Micro Devices, Inc. Method of forming a CMOS transistor having ultra shallow source and drain regions
US6265293B1 (en) 1999-08-27 2001-07-24 Advanced Micro Devices, Inc. CMOS transistors fabricated in optimized RTA scheme
US6284630B1 (en) * 1999-10-20 2001-09-04 Advanced Micro Devices, Inc. Method for fabrication of abrupt drain and source extensions for a field effect transistor
US6090651A (en) * 1999-11-05 2000-07-18 Lsi Logic Corporation Depletion free polysilicon gate electrodes
US6586318B1 (en) * 1999-12-28 2003-07-01 Xerox Corporation Thin phosphorus nitride film as an N-type doping source used in laser doping technology
US6570656B1 (en) 2000-04-10 2003-05-27 Ultratech Stepper, Inc. Illumination fluence regulation system and method for use in thermal processing employed in the fabrication of reduced-dimension integrated circuits
US6645838B1 (en) 2000-04-10 2003-11-11 Ultratech Stepper, Inc. Selective absorption process for forming an activated doped region in a semiconductor
US6380044B1 (en) * 2000-04-12 2002-04-30 Ultratech Stepper, Inc. High-speed semiconductor transistor and selective absorption process forming same
US6294415B1 (en) * 2000-04-26 2001-09-25 United Microelectronics Corp. Method of fabricating a MOS transistor
US6635588B1 (en) 2000-06-12 2003-10-21 Ultratech Stepper, Inc. Method for laser thermal processing using thermally induced reflectivity switch
US6303476B1 (en) 2000-06-12 2001-10-16 Ultratech Stepper, Inc. Thermally induced reflectivity switch for laser thermal processing
US6399450B1 (en) 2000-07-05 2002-06-04 Advanced Micro Devices, Inc. Low thermal budget process for manufacturing MOS transistors having elevated source and drain regions
US6335253B1 (en) 2000-07-12 2002-01-01 Chartered Semiconductor Manufacturing Ltd. Method to form MOS transistors with shallow junctions using laser annealing
US6630386B1 (en) 2000-07-18 2003-10-07 Advanced Micro Devices, Inc CMOS manufacturing process with self-amorphized source/drain junctions and extensions
JP2002050764A (ja) * 2000-08-02 2002-02-15 Matsushita Electric Ind Co Ltd 薄膜トランジスタ、アレイ基板、液晶表示装置、有機ｅｌ表示装置およびその製造方法
US6521502B1 (en) 2000-08-07 2003-02-18 Advanced Micro Devices, Inc. Solid phase epitaxy activation process for source/drain junction extensions and halo regions
US6479821B1 (en) 2000-09-11 2002-11-12 Ultratech Stepper, Inc. Thermally induced phase switch for laser thermal processing
US6365476B1 (en) 2000-10-27 2002-04-02 Ultratech Stepper, Inc. Laser thermal process for fabricating field-effect transistors
US6594446B2 (en) 2000-12-04 2003-07-15 Vortek Industries Ltd. Heat-treating methods and systems
US6970644B2 (en) * 2000-12-21 2005-11-29 Mattson Technology, Inc. Heating configuration for use in thermal processing chambers
US7015422B2 (en) 2000-12-21 2006-03-21 Mattson Technology, Inc. System and process for heating semiconductor wafers by optimizing absorption of electromagnetic energy
US6495437B1 (en) 2001-02-09 2002-12-17 Advanced Micro Devices, Inc. Low temperature process to locally form high-k gate dielectrics
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6787424B1 (en) 2001-02-09 2004-09-07 Advanced Micro Devices, Inc. Fully depleted SOI transistor with elevated source and drain
US6756277B1 (en) 2001-02-09 2004-06-29 Advanced Micro Devices, Inc. Replacement gate process for transistors having elevated source and drain regions
US6551885B1 (en) 2001-02-09 2003-04-22 Advanced Micro Devices, Inc. Low temperature process for a thin film transistor
JP3904936B2 (ja) * 2001-03-02 2007-04-11 富士通株式会社 半導体装置の製造方法
US6387784B1 (en) 2001-03-19 2002-05-14 Chartered Semiconductor Manufacturing Ltd. Method to reduce polysilicon depletion in MOS transistors
US6885078B2 (en) * 2001-11-09 2005-04-26 Lsi Logic Corporation Circuit isolation utilizing MeV implantation
US6555439B1 (en) * 2001-12-18 2003-04-29 Advanced Micro Devices, Inc. Partial recrystallization of source/drain region before laser thermal annealing
JP2005515425A (ja) 2001-12-26 2005-05-26 ボルテック インダストリーズ リミテッド 温度測定および熱処理方法およびシステム
KR100940530B1 (ko) * 2003-01-17 2010-02-10 삼성전자주식회사 실리콘 광소자 제조방법 및 이에 의해 제조된 실리콘광소자 및 이를 적용한 화상 입력 및/또는 출력장치
KR100446622B1 (ko) * 2002-01-10 2004-09-04 삼성전자주식회사 실리콘 광소자 및 이를 적용한 발광 디바이스 장치
US6723634B1 (en) * 2002-03-14 2004-04-20 Advanced Micro Devices, Inc. Method of forming interconnects with improved barrier layer adhesion
KR20120045040A (ko) 2002-12-20 2012-05-08 맷슨 테크날러지 캐나다 인코퍼레이티드 피가공물 지지 방법
TW200423185A (en) 2003-02-19 2004-11-01 Matsushita Electric Industrial Co Ltd Method of introducing impurity
US6803270B2 (en) * 2003-02-21 2004-10-12 International Business Machines Corporation CMOS performance enhancement using localized voids and extended defects
US6844250B1 (en) 2003-03-13 2005-01-18 Ultratech, Inc. Method and system for laser thermal processing of semiconductor devices
US7759254B2 (en) 2003-08-25 2010-07-20 Panasonic Corporation Method for forming impurity-introduced layer, method for cleaning object to be processed apparatus for introducing impurity and method for producing device
TW200520063A (en) 2003-10-09 2005-06-16 Matsushita Electric Industrial Co Ltd Junction-forming method and object to be processed and formed by using the same
US7166528B2 (en) * 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
WO2005059991A1 (en) 2003-12-19 2005-06-30 Mattson Technology Canada Inc. Apparatuses and methods for suppressing thermally induced motion of a workpiece
US7112499B2 (en) * 2004-01-16 2006-09-26 Chartered Semiconductor Manufacturing Ltd. Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal
US7312125B1 (en) 2004-02-05 2007-12-25 Advanced Micro Devices, Inc. Fully depleted strained semiconductor on insulator transistor and method of making the same
US7078302B2 (en) * 2004-02-23 2006-07-18 Applied Materials, Inc. Gate electrode dopant activation method for semiconductor manufacturing including a laser anneal
CN1965391A (zh) 2004-05-14 2007-05-16 松下电器产业株式会社 制造半导体器件的方法和设备
KR100612875B1 (ko) * 2004-11-24 2006-08-14 삼성전자주식회사 실리콘 광소자 제조방법 및 이에 의해 제조된 실리콘광소자 및 이를 적용한 화상 입력 및/또는 출력장치
KR20060059327A (ko) * 2004-11-27 2006-06-01 삼성전자주식회사 실리콘 광소자 제조방법 및 이에 의해 제조된 실리콘광소자 및 이를 적용한 화상 입력 및/또는 출력장치
US7235492B2 (en) * 2005-01-31 2007-06-26 Applied Materials, Inc. Low temperature etchant for treatment of silicon-containing surfaces
US7172954B2 (en) * 2005-05-05 2007-02-06 Infineon Technologies Ag Implantation process in semiconductor fabrication
WO2007035660A1 (en) * 2005-09-20 2007-03-29 Applied Materials, Inc. Method to form a device on a soi substrate
US7585763B2 (en) * 2005-11-07 2009-09-08 Samsung Electronics Co., Ltd. Methods of fabricating integrated circuit devices using anti-reflective coating as implant blocking layer
CN101356632A (zh) * 2006-01-13 2009-01-28 富士通株式会社 半导体器件的制造方法
JP2008078166A (ja) * 2006-09-19 2008-04-03 Sony Corp 薄膜半導体装置の製造方法および薄膜半導体装置
JP5967859B2 (ja) 2006-11-15 2016-08-10 マトソン テクノロジー、インコーポレイテッド 熱処理中の被加工物を支持するシステムおよび方法
DE102007020261B4 (de) * 2007-04-30 2009-07-16 Advanced Micro Devices, Inc., Sunnyvale Verfahren zur Erhöhung der Dotierstoffaktivierung unter Anwendung mehrerer sequenzieller fortschrittlicher Laser/Blitzlicht-Ausheizprozesse
US20090263944A1 (en) * 2008-04-17 2009-10-22 Albert Chin Method for making low Vt gate-first light-reflective-layer covered dual metal-gates on high-k CMOSFETs
CN102089873A (zh) 2008-05-16 2011-06-08 加拿大马特森技术有限公司 工件破损防止方法及设备
DE112010004296T5 (de) 2009-11-06 2013-01-03 Hitachi, Ltd. Verfahren zur Herstellung einer Halbleitervorrichtung
US8399808B2 (en) 2010-10-22 2013-03-19 Ultratech, Inc. Systems and methods for forming a time-averaged line image
US8026519B1 (en) 2010-10-22 2011-09-27 Ultratech, Inc. Systems and methods for forming a time-averaged line image
US9302348B2 (en) 2011-06-07 2016-04-05 Ultratech Inc. Ultrafast laser annealing with reduced pattern density effects in integrated circuit fabrication
US8309474B1 (en) 2011-06-07 2012-11-13 Ultratech, Inc. Ultrafast laser annealing with reduced pattern density effects in integrated circuit fabrication
US8546805B2 (en) 2012-01-27 2013-10-01 Ultratech, Inc. Two-beam laser annealing with improved temperature performance
US8501638B1 (en) 2012-04-27 2013-08-06 Ultratech, Inc. Laser annealing scanning methods with reduced annealing non-uniformities
US9558973B2 (en) 2012-06-11 2017-01-31 Ultratech, Inc. Laser annealing systems and methods with ultra-short dwell times
SG10201503478UA (en) 2012-06-11 2015-06-29 Ultratech Inc Laser annealing systems and methods with ultra-short dwell times
JP2013258188A (ja) * 2012-06-11 2013-12-26 Hitachi Kokusai Electric Inc 基板処理方法と半導体装置の製造方法、および基板処理装置
US9490128B2 (en) 2012-08-27 2016-11-08 Ultratech, Inc. Non-melt thin-wafer laser thermal annealing methods
CN103050387B (zh) * 2012-12-18 2016-06-08 上海华虹宏力半导体制造有限公司 硅背面的离子注入方法
DE112013007003T5 (de) * 2013-06-20 2016-01-07 Intel Corporation Nicht planare Halbleitervorrichtung mit dotierter Unterrippenregion und Verfahren zu deren Herstellung
US9343307B2 (en) 2013-12-24 2016-05-17 Ultratech, Inc. Laser spike annealing using fiber lasers
JP6193305B2 (ja) 2014-07-29 2017-09-06 ウルトラテック インク 高性能線形成光学システム及び方法
US10083843B2 (en) 2014-12-17 2018-09-25 Ultratech, Inc. Laser annealing systems and methods with ultra-short dwell times

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4617066A (en) * 1984-11-26 1986-10-14 Hughes Aircraft Company Process of making semiconductors having shallow, hyperabrupt doped regions by implantation and two step annealing
US4904611A (en) * 1987-09-18 1990-02-27 Xerox Corporation Formation of large grain polycrystalline films
US5342793A (en) * 1990-02-20 1994-08-30 Sgs-Thomson Microelectronics, S.R.L. Process for obtaining multi-layer metallization of the back of a semiconductor substrate
US5147826A (en) * 1990-08-06 1992-09-15 The Pennsylvania Research Corporation Low temperature crystallization and pattering of amorphous silicon films
JPH0521448A (ja) * 1991-07-10 1993-01-29 Sharp Corp 半導体装置の製造方法
KR970006723B1 (ko) * 1993-09-07 1997-04-29 한국과학기술원 입자 크기가 큰 다결정 규소 박막의 제조방법
KR970006262B1 (ko) * 1994-02-04 1997-04-25 금성일렉트론 주식회사 도우핑된 디스포저블층(disposable layer)을 이용한 모스트랜지스터의 제조방법
DE19505818A1 (de) * 1995-02-09 1995-09-07 Ulrich Prof Dr Mohr Verfahren zum Dotieren von Halbleiterkristallen, insbesondere von Siliziumkristallen

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7932185B2 (en) 2003-06-02 2011-04-26 Sumitomo Heavy Industries, Ltd. Process for fabricating semiconductor device

Also Published As

Publication number Publication date
US5908307A (en) 1999-06-01
EP1012879A2 (en) 2000-06-28
EP1012879A4 (en) 2000-06-28
WO1998034268A2 (en) 1998-08-06
KR100511765B1 (ko) 2005-09-05
EP1012879B1 (en) 2002-09-04
DE69807718D1 (de) 2002-10-10
DE69807718T2 (de) 2003-07-31
WO1998034268A3 (en) 1999-02-18
KR20000070658A (ko) 2000-11-25

Similar Documents

Publication Publication Date Title
JP2001509316A (ja) 低減寸法集積回路の製造法
US5956603A (en) Gas immersion laser annealing method suitable for use in the fabrication of reduced-dimension integrated circuits
Kim et al. Advanced source/drain engineering for box-shaped ultrashallow junction formation using laser annealing and pre-amorphization implantation in sub-100-nm SOI CMOS
US6380044B1 (en) High-speed semiconductor transistor and selective absorption process forming same
EP0976147B1 (en) Method for forming a silicide region on a silicon body
US6777317B2 (en) Method for semiconductor gate doping
US6365476B1 (en) Laser thermal process for fabricating field-effect transistors
US5399506A (en) Semiconductor fabricating process
US6274488B1 (en) Method of forming a silicide region in a Si substrate and a device having same
US6387803B2 (en) Method for forming a silicide region on a silicon body
US6645838B1 (en) Selective absorption process for forming an activated doped region in a semiconductor
JP3277533B2 (ja) 半導体装置の製造方法
JP2005510871A (ja) 半導体装置の製造方法
JP2005510871A5 (https=)
US7112499B2 (en) Dual step source/drain extension junction anneal to reduce the junction depth: multiple-pulse low energy laser anneal coupled with rapid thermal anneal
US20020086502A1 (en) Method of forming a doped region in a semiconductor material
JP2002246329A (ja) 半導体基板の極浅ｐｎ接合の形成方法
Shima et al. Ultrashallow junction formation by self-limiting LTP and its application to sub-65-nm node MOSFETs
JP2808749B2 (ja) 半導体基板への接合形成方法
JP5103695B2 (ja) 電界効果型半導体装置の製造方法
JP2821628B2 (ja) 半導体装置の製造方法
Matsuno et al. Effect of pulse duration on formation of ultrashallow junction by excimer laser annealing
EP1780776A1 (en) Process for manufacturing a high-scale-integration mos device

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050126

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20050126

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20081021

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20090115

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20090302

A313 Final decision of rejection without a dissenting response from the applicant

Free format text: JAPANESE INTERMEDIATE CODE: A313

Effective date: 20090511

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20090616