JP2001102447A - コンタクト構造の製造方法 - Google Patents

コンタクト構造の製造方法

Info

Publication number
JP2001102447A
JP2001102447A JP27792299A JP27792299A JP2001102447A JP 2001102447 A JP2001102447 A JP 2001102447A JP 27792299 A JP27792299 A JP 27792299A JP 27792299 A JP27792299 A JP 27792299A JP 2001102447 A JP2001102447 A JP 2001102447A
Authority
JP
Japan
Prior art keywords
insulating film
interlayer insulating
film
etching
dielectric constant
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP27792299A
Other languages
English (en)
Japanese (ja)
Other versions
JP2001102447A5 (https=
Inventor
Masazumi Matsuura
正純 松浦
Kinya Goto
欣哉 後藤
Noboru Morimoto
昇 森本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP27792299A priority Critical patent/JP2001102447A/ja
Priority to US09/663,201 priority patent/US6399424B1/en
Publication of JP2001102447A publication Critical patent/JP2001102447A/ja
Publication of JP2001102447A5 publication Critical patent/JP2001102447A5/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP27792299A 1999-09-30 1999-09-30 コンタクト構造の製造方法 Pending JP2001102447A (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP27792299A JP2001102447A (ja) 1999-09-30 1999-09-30 コンタクト構造の製造方法
US09/663,201 US6399424B1 (en) 1999-09-30 2000-09-18 Method of manufacturing contact structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP27792299A JP2001102447A (ja) 1999-09-30 1999-09-30 コンタクト構造の製造方法

Publications (2)

Publication Number Publication Date
JP2001102447A true JP2001102447A (ja) 2001-04-13
JP2001102447A5 JP2001102447A5 (https=) 2006-10-26

Family

ID=17590164

Family Applications (1)

Application Number Title Priority Date Filing Date
JP27792299A Pending JP2001102447A (ja) 1999-09-30 1999-09-30 コンタクト構造の製造方法

Country Status (2)

Country Link
US (1) US6399424B1 (https=)
JP (1) JP2001102447A (https=)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002343858A (ja) * 2001-05-11 2002-11-29 Sony Corp 半導体装置およびその製造方法
WO2002097852A3 (en) * 2001-03-30 2003-04-03 Lam Res Corp Plasma etching of silicon carbide
JP2003163264A (ja) * 2001-09-28 2003-06-06 Sharp Corp エアギャップの銅のインタコネクト
US6841467B2 (en) 2000-04-25 2005-01-11 Sharp Kabushiki Kaisha Method for producing semiconductor device
US7084070B1 (en) 2001-03-30 2006-08-01 Lam Research Corporation Treatment for corrosion in substrate processing

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4858895B2 (ja) * 2000-07-21 2012-01-18 富士通セミコンダクター株式会社 半導体装置の製造方法
US6689682B1 (en) * 2000-08-11 2004-02-10 Advanced Micro Devices, Inc. Multilayer anti-reflective coating for semiconductor lithography
US6713874B1 (en) * 2001-03-27 2004-03-30 Advanced Micro Devices, Inc. Semiconductor devices with dual nature capping/arc layers on organic-doped silica glass inter-layer dielectrics
US7226853B2 (en) * 2001-12-26 2007-06-05 Applied Materials, Inc. Method of forming a dual damascene structure utilizing a three layer hard mask structure

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232098A (ja) * 1993-02-05 1994-08-19 Sony Corp 酸化防止方法およびドライエッチング方法
JPH11251294A (ja) * 1998-02-27 1999-09-17 Sony Corp 半導体装置の製造方法
EP0945900A1 (en) * 1998-03-26 1999-09-29 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
JP2000124306A (ja) * 1998-10-14 2000-04-28 Fujitsu Ltd 半導体装置及びその製造方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62144342A (ja) 1985-12-19 1987-06-27 Oki Electric Ind Co Ltd 多層配線のコンタクトホ−ル形成方法
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure
JP3300643B2 (ja) 1997-09-09 2002-07-08 株式会社東芝 半導体装置の製造方法
US6194128B1 (en) * 1998-09-17 2001-02-27 Taiwan Semiconductor Manufacturing Company Method of dual damascene etching
US6110648A (en) * 1998-09-17 2000-08-29 Taiwan Semiconductor Manufacturing Company Method of enclosing copper conductor in a dual damascene process
US6187663B1 (en) * 1999-01-19 2001-02-13 Taiwan Semiconductor Manufacturing Company Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials
US6235653B1 (en) * 1999-06-04 2001-05-22 Taiwan Semiconductor Manufacturing Company Ar-based si-rich oxynitride film for dual damascene and/or contact etch stop layer
US6331479B1 (en) * 1999-09-20 2001-12-18 Chartered Semiconductor Manufacturing Ltd. Method to prevent degradation of low dielectric constant material in copper damascene interconnects

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06232098A (ja) * 1993-02-05 1994-08-19 Sony Corp 酸化防止方法およびドライエッチング方法
JPH11251294A (ja) * 1998-02-27 1999-09-17 Sony Corp 半導体装置の製造方法
EP0945900A1 (en) * 1998-03-26 1999-09-29 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
JP2000124306A (ja) * 1998-10-14 2000-04-28 Fujitsu Ltd 半導体装置及びその製造方法

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6841467B2 (en) 2000-04-25 2005-01-11 Sharp Kabushiki Kaisha Method for producing semiconductor device
WO2002097852A3 (en) * 2001-03-30 2003-04-03 Lam Res Corp Plasma etching of silicon carbide
US6919278B2 (en) 2001-03-30 2005-07-19 Lam Research Corporation Method for etching silicon carbide
US7084070B1 (en) 2001-03-30 2006-08-01 Lam Research Corporation Treatment for corrosion in substrate processing
US7166535B2 (en) 2001-03-30 2007-01-23 Lam Research Corporation Plasma etching of silicon carbide
JP2002343858A (ja) * 2001-05-11 2002-11-29 Sony Corp 半導体装置およびその製造方法
JP2003163264A (ja) * 2001-09-28 2003-06-06 Sharp Corp エアギャップの銅のインタコネクト

Also Published As

Publication number Publication date
US6399424B1 (en) 2002-06-04

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