JP2001077215A5 - - Google Patents

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Publication number
JP2001077215A5
JP2001077215A5 JP1999250780A JP25078099A JP2001077215A5 JP 2001077215 A5 JP2001077215 A5 JP 2001077215A5 JP 1999250780 A JP1999250780 A JP 1999250780A JP 25078099 A JP25078099 A JP 25078099A JP 2001077215 A5 JP2001077215 A5 JP 2001077215A5
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JP
Japan
Prior art keywords
insulating film
semiconductor substrate
film
forming
impurity diffusion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1999250780A
Other languages
English (en)
Japanese (ja)
Other versions
JP3958899B2 (ja
JP2001077215A (ja
Filing date
Publication date
Application filed filed Critical
Priority to JP25078099A priority Critical patent/JP3958899B2/ja
Priority claimed from JP25078099A external-priority patent/JP3958899B2/ja
Priority to KR1020027002754A priority patent/KR100727445B1/ko
Priority to PCT/JP2000/003468 priority patent/WO2001018878A1/ja
Publication of JP2001077215A publication Critical patent/JP2001077215A/ja
Priority to US10/085,023 priority patent/US6750520B2/en
Publication of JP2001077215A5 publication Critical patent/JP2001077215A5/ja
Application granted granted Critical
Publication of JP3958899B2 publication Critical patent/JP3958899B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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JP25078099A 1999-09-03 1999-09-03 半導体記憶装置及びその製造方法 Expired - Fee Related JP3958899B2 (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP25078099A JP3958899B2 (ja) 1999-09-03 1999-09-03 半導体記憶装置及びその製造方法
KR1020027002754A KR100727445B1 (ko) 1999-09-03 2000-05-30 반도체 기억장치 및 그 제조 방법
PCT/JP2000/003468 WO2001018878A1 (fr) 1999-09-03 2000-05-30 Memoire a semi-conducteurs et procede de fabrication de celle-ci
US10/085,023 US6750520B2 (en) 1999-09-03 2002-03-01 Two-bit semiconductor memory with enhanced carrier trapping

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25078099A JP3958899B2 (ja) 1999-09-03 1999-09-03 半導体記憶装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2001077215A JP2001077215A (ja) 2001-03-23
JP2001077215A5 true JP2001077215A5 (enExample) 2004-12-09
JP3958899B2 JP3958899B2 (ja) 2007-08-15

Family

ID=17212945

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25078099A Expired - Fee Related JP3958899B2 (ja) 1999-09-03 1999-09-03 半導体記憶装置及びその製造方法

Country Status (4)

Country Link
US (1) US6750520B2 (enExample)
JP (1) JP3958899B2 (enExample)
KR (1) KR100727445B1 (enExample)
WO (1) WO2001018878A1 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4923321B2 (ja) * 2000-09-12 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置の動作方法
SG95637A1 (en) 2001-03-15 2003-04-23 Micron Technology Inc Semiconductor/printed circuit board assembly, and computer system
JP4670187B2 (ja) * 2001-06-06 2011-04-13 ソニー株式会社 不揮発性半導体メモリ装置
DE10201304A1 (de) 2002-01-15 2003-07-31 Infineon Technologies Ag Nichtflüchtige Halbleiter -Speicherzelle sowie zugehöriges Herstellungsverfahren
US6614694B1 (en) * 2002-04-02 2003-09-02 Macronix International Co., Ltd. Erase scheme for non-volatile memory
JP3664159B2 (ja) * 2002-10-29 2005-06-22 セイコーエプソン株式会社 半導体装置およびその製造方法
JP2004266185A (ja) * 2003-03-04 2004-09-24 Renesas Technology Corp 半導体装置およびその製造方法
JP5162129B2 (ja) * 2004-06-14 2013-03-13 スパンション エルエルシー 半導体装置
JP4872395B2 (ja) * 2006-03-15 2012-02-08 ヤマハ株式会社 シリコン酸化膜形成法、容量素子の製法及び半導体装置の製法
JP2008053270A (ja) * 2006-08-22 2008-03-06 Nec Electronics Corp 半導体記憶装置、及びその製造方法
JP2008227403A (ja) * 2007-03-15 2008-09-25 Spansion Llc 半導体装置およびその製造方法
US8283224B2 (en) * 2008-12-23 2012-10-09 Texas Instruments Incorporated Ammonia pre-treatment in the fabrication of a memory cell
JP5552521B2 (ja) * 2012-11-09 2014-07-16 スパンション エルエルシー 半導体装置の製造方法
US10290352B2 (en) * 2015-02-27 2019-05-14 Qualcomm Incorporated System, apparatus, and method of programming a one-time programmable memory circuit having dual programming regions

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4873086A (enExample) * 1971-11-24 1973-10-02
DE2932712A1 (de) 1979-08-13 1981-03-26 Basf Ag, 67063 Ludwigshafen Verfahren zur gewinnung von imidazolen
JPS5632464U (enExample) * 1979-08-17 1981-03-30
JPS60161674A (ja) * 1984-02-02 1985-08-23 Matsushita Electronics Corp 半導体記憶装置
US5143860A (en) * 1987-12-23 1992-09-01 Texas Instruments Incorporated High density EPROM fabricaiton method having sidewall floating gates
JPH05145080A (ja) * 1991-11-25 1993-06-11 Kawasaki Steel Corp 不揮発性記憶装置
JP3397903B2 (ja) 1994-08-23 2003-04-21 新日本製鐵株式会社 不揮発性半導体記憶装置の製造方法
KR100187656B1 (ko) 1995-05-16 1999-06-01 김주용 플래쉬 이이피롬 셀의 제조방법 및 그 프로그램 방법
US5768192A (en) * 1996-07-23 1998-06-16 Saifun Semiconductors, Ltd. Non-volatile semiconductor memory cell utilizing asymmetrical charge trapping
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

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