JP2000150701A - 半導体装置並びにこれに用いる接続用基板及びその製造方法 - Google Patents

半導体装置並びにこれに用いる接続用基板及びその製造方法

Info

Publication number
JP2000150701A
JP2000150701A JP10314723A JP31472398A JP2000150701A JP 2000150701 A JP2000150701 A JP 2000150701A JP 10314723 A JP10314723 A JP 10314723A JP 31472398 A JP31472398 A JP 31472398A JP 2000150701 A JP2000150701 A JP 2000150701A
Authority
JP
Japan
Prior art keywords
insulating substrate
solder
hole
copper foil
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10314723A
Other languages
English (en)
Japanese (ja)
Inventor
Michio Horiuchi
道夫 堀内
Takuya Kazama
拓也 風間
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP10314723A priority Critical patent/JP2000150701A/ja
Priority to KR1019990048410A priority patent/KR20000035210A/ko
Priority to US09/434,113 priority patent/US6236112B1/en
Publication of JP2000150701A publication Critical patent/JP2000150701A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05573—Single external layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
JP10314723A 1998-11-05 1998-11-05 半導体装置並びにこれに用いる接続用基板及びその製造方法 Pending JP2000150701A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP10314723A JP2000150701A (ja) 1998-11-05 1998-11-05 半導体装置並びにこれに用いる接続用基板及びその製造方法
KR1019990048410A KR20000035210A (ko) 1998-11-05 1999-11-03 반도체 장치, 반도체 장치용 접속용 기판, 및 접속용기판의 제조 방법
US09/434,113 US6236112B1 (en) 1998-11-05 1999-11-05 Semiconductor device, connecting substrate therefor, and process of manufacturing connecting substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10314723A JP2000150701A (ja) 1998-11-05 1998-11-05 半導体装置並びにこれに用いる接続用基板及びその製造方法

Publications (1)

Publication Number Publication Date
JP2000150701A true JP2000150701A (ja) 2000-05-30

Family

ID=18056804

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10314723A Pending JP2000150701A (ja) 1998-11-05 1998-11-05 半導体装置並びにこれに用いる接続用基板及びその製造方法

Country Status (3)

Country Link
US (1) US6236112B1 (ko)
JP (1) JP2000150701A (ko)
KR (1) KR20000035210A (ko)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005123548A (ja) * 2003-09-24 2005-05-12 Ibiden Co Ltd インターポーザ、多層プリント配線板
WO2006004127A1 (ja) * 2004-07-06 2006-01-12 Tokyo Electron Limited インターポーザおよびインターポーザの製造方法
JP2006190771A (ja) * 2005-01-05 2006-07-20 Renesas Technology Corp 半導体装置
CN100413058C (zh) * 2004-07-06 2008-08-20 东京毅力科创株式会社 互连导电层及互连导电层的制造方法
KR101232208B1 (ko) 2009-09-03 2013-02-12 한국전자통신연구원 반도체 소자 적층 패키지 및 그 형성 방법
US20160027755A1 (en) * 2013-03-14 2016-01-28 Ps4 Luxco S.A.R.L. Semiconductor chip and semiconductor device provided with semiconductor chip

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IL120866A0 (en) * 1997-05-20 1997-09-30 Micro Components Systems Ltd Process for producing an aluminum substrate
IL127256A (en) 1998-11-25 2002-09-12 Micro Components Ltd A device for packaging electronic components, a process for its manufacture and a pin device used in the process
JP3287328B2 (ja) * 1999-03-09 2002-06-04 日本電気株式会社 半導体装置及び半導体装置の製造方法
JP3498634B2 (ja) * 1999-05-31 2004-02-16 関西日本電気株式会社 半導体装置の製造方法
US6510976B2 (en) * 2001-05-18 2003-01-28 Advanpack Solutions Pte. Ltd. Method for forming a flip chip semiconductor package
KR100401516B1 (ko) 2001-08-30 2003-10-17 주식회사 하이닉스반도체 런너 메탈을 갖는 패키지의 제조방법
JP3927783B2 (ja) * 2001-10-16 2007-06-13 新光電気工業株式会社 半導体部品
TWI256719B (en) * 2002-03-06 2006-06-11 Via Tech Inc Semiconductor device package module and manufacturing method thereof
US7122404B2 (en) * 2003-03-11 2006-10-17 Micron Technology, Inc. Techniques for packaging a multiple device component
US20040188696A1 (en) * 2003-03-28 2004-09-30 Gelcore, Llc LED power package
JP3835460B2 (ja) * 2004-04-08 2006-10-18 セイコーエプソン株式会社 電子部品実装体の製造方法、及び電気光学装置
FR2876243B1 (fr) * 2004-10-04 2007-01-26 Commissariat Energie Atomique Composant a protuberances conductrices ductiles enterrees et procede de connexion electrique entre ce composant et un composant muni de pointes conductrices dures
JP2008211125A (ja) * 2007-02-28 2008-09-11 Spansion Llc 半導体装置およびその製造方法
US8030768B2 (en) * 2007-04-24 2011-10-04 United Test And Assembly Center Ltd. Semiconductor package with under bump metallization aligned with open vias
DE102008025491A1 (de) * 2008-05-28 2009-12-03 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauteil und Leiterplatte
JP6092729B2 (ja) * 2013-07-19 2017-03-08 新光電気工業株式会社 プローブカード及びその製造方法
JP6208486B2 (ja) * 2013-07-19 2017-10-04 新光電気工業株式会社 プローブカード及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0656861B2 (ja) 1986-06-13 1994-07-27 日本電信電話株式会社 基板間接続子の製造法
JP2837521B2 (ja) 1990-07-25 1998-12-16 株式会社日立製作所 半導体集積回路装置およびその配線変更方法
JPH04154136A (ja) 1990-10-18 1992-05-27 Fujitsu Ltd ベアチップの実装方法
US5258648A (en) * 1991-06-27 1993-11-02 Motorola, Inc. Composite flip chip semiconductor device with an interposer having test contacts formed along its periphery
US5789278A (en) * 1996-07-30 1998-08-04 Micron Technology, Inc. Method for fabricating chip modules

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005123548A (ja) * 2003-09-24 2005-05-12 Ibiden Co Ltd インターポーザ、多層プリント配線板
WO2006004127A1 (ja) * 2004-07-06 2006-01-12 Tokyo Electron Limited インターポーザおよびインターポーザの製造方法
KR100786156B1 (ko) * 2004-07-06 2007-12-18 동경 엘렉트론 주식회사 인터포저 및 인터포저의 제조 방법
KR100786166B1 (ko) * 2004-07-06 2007-12-21 동경 엘렉트론 주식회사 인터포저 및 인터포저의 제조 방법
CN100413058C (zh) * 2004-07-06 2008-08-20 东京毅力科创株式会社 互连导电层及互连导电层的制造方法
JP2006190771A (ja) * 2005-01-05 2006-07-20 Renesas Technology Corp 半導体装置
KR101232208B1 (ko) 2009-09-03 2013-02-12 한국전자통신연구원 반도체 소자 적층 패키지 및 그 형성 방법
US20160027755A1 (en) * 2013-03-14 2016-01-28 Ps4 Luxco S.A.R.L. Semiconductor chip and semiconductor device provided with semiconductor chip
US10115693B2 (en) * 2013-03-14 2018-10-30 Longitude Licensing Limited Solder layer of a semiconductor chip arranged within recesses
US10734322B2 (en) 2013-03-14 2020-08-04 Longitude Licensing Limited Through-holes of a semiconductor chip

Also Published As

Publication number Publication date
US6236112B1 (en) 2001-05-22
KR20000035210A (ko) 2000-06-26

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