ITMI913080A1 - Dispositivo di memoria a semiconduttore avente due matrici di memoria eseguenti trasmissione e ricezione mutua di dati - Google Patents

Dispositivo di memoria a semiconduttore avente due matrici di memoria eseguenti trasmissione e ricezione mutua di dati

Info

Publication number
ITMI913080A1
ITMI913080A1 IT003080A ITMI913080A ITMI913080A1 IT MI913080 A1 ITMI913080 A1 IT MI913080A1 IT 003080 A IT003080 A IT 003080A IT MI913080 A ITMI913080 A IT MI913080A IT MI913080 A1 ITMI913080 A1 IT MI913080A1
Authority
IT
Italy
Prior art keywords
transmission
data
memory device
matrices
semiconductor memory
Prior art date
Application number
IT003080A
Other languages
English (en)
Inventor
Yoshio Fudeyasu
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI913080A0 publication Critical patent/ITMI913080A0/it
Publication of ITMI913080A1 publication Critical patent/ITMI913080A1/it
Application granted granted Critical
Publication of IT1252271B publication Critical patent/IT1252271B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1093—Input synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Multimedia (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
ITMI913080A 1990-11-20 1991-11-19 Dispositivo di memoria a semiconduttore avente due matrici di memoria eseguenti trasmissione e ricezione mutua di dati IT1252271B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2316849A JP2604276B2 (ja) 1990-11-20 1990-11-20 半導体記憶装置

Publications (3)

Publication Number Publication Date
ITMI913080A0 ITMI913080A0 (it) 1991-11-19
ITMI913080A1 true ITMI913080A1 (it) 1993-05-19
IT1252271B IT1252271B (it) 1995-06-08

Family

ID=18081606

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI913080A IT1252271B (it) 1990-11-20 1991-11-19 Dispositivo di memoria a semiconduttore avente due matrici di memoria eseguenti trasmissione e ricezione mutua di dati

Country Status (5)

Country Link
US (1) US5327386A (it)
JP (1) JP2604276B2 (it)
KR (1) KR950006334B1 (it)
DE (1) DE4138102C2 (it)
IT (1) IT1252271B (it)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2741825B2 (ja) * 1992-04-28 1998-04-22 三菱電機株式会社 半導体記憶装置
US5299159A (en) * 1992-06-29 1994-03-29 Texas Instruments Incorporated Serial register stage arranged for connection with a single bitline
EP0579862A1 (de) * 1992-07-24 1994-01-26 Siemens Aktiengesellschaft Integrierte Halbleiterspeicheranordnung
US5592634A (en) * 1994-05-16 1997-01-07 Motorola Inc. Zero-cycle multi-state branch cache prediction data processing system and method thereof
KR0165159B1 (ko) * 1994-07-28 1999-02-01 사또 후미오 반도체 기억 장치
KR0144058B1 (ko) * 1995-03-28 1998-08-17 문정환 시리얼 억세스 메모리 제어 회로
WO1997023877A1 (fr) * 1995-12-25 1997-07-03 Oki Electric Industry Co., Ltd. Memoire a semiconducteur amelioree a decodeur d'adresse de ligne fournissant les signaux de selection de ligne et son procede de commande
US5765214A (en) * 1996-04-22 1998-06-09 Cypress Semiconductor Corporation Memory access method and apparatus and multi-plane memory device with prefetch
US5917769A (en) * 1997-08-12 1999-06-29 Lucent Technologies Inc. Method and system rotating data in a memory array device
DE19910060A1 (de) * 1999-03-08 2000-09-21 Audi Ag Windschotteinrichtung für ein Fahrzeug
US7171508B2 (en) * 2004-08-23 2007-01-30 Micron Technology, Inc. Dual port memory with asymmetric inputs and outputs, device, system and method
JP2006262197A (ja) * 2005-03-17 2006-09-28 Fujitsu Ltd 位相制御回路
US10586598B2 (en) * 2017-09-14 2020-03-10 Silicon Storage Technology, Inc. System and method for implementing inference engine by optimizing programming operation

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60252979A (ja) * 1984-05-30 1985-12-13 Oki Electric Ind Co Ltd Ｃｍｏｓ入出力回路
JPS61104391A (ja) * 1984-10-23 1986-05-22 Fujitsu Ltd 半導体記憶装置
JPH0793009B2 (ja) * 1984-12-13 1995-10-09 株式会社東芝 半導体記憶装置
JPS62165785A (ja) * 1986-01-17 1987-07-22 Mitsubishi Electric Corp 半導体記憶装置
JP2501344B2 (ja) * 1987-12-26 1996-05-29 株式会社東芝 デ―タ転送回路
US4873665A (en) * 1988-06-07 1989-10-10 Dallas Semiconductor Corporation Dual storage cell memory including data transfer circuits
JP2837682B2 (ja) * 1989-01-13 1998-12-16 株式会社日立製作所 半導体記憶装置
US5146428A (en) * 1989-02-07 1992-09-08 Hitachi, Ltd. Single chip gate array
DE69023258T2 (de) * 1989-03-15 1996-05-15 Matsushita Electronics Corp Halbleiter-Speichereinrichtung.
US5040146A (en) * 1989-04-21 1991-08-13 Siemens Aktiengesellschaft Static memory cell
US4964081A (en) * 1989-08-11 1990-10-16 Cray Research, Inc. Read-while-write ram cell

Also Published As

Publication number Publication date
DE4138102C2 (de) 1994-01-13
JP2604276B2 (ja) 1997-04-30
ITMI913080A0 (it) 1991-11-19
US5327386A (en) 1994-07-05
DE4138102A1 (de) 1992-05-21
IT1252271B (it) 1995-06-08
KR950006334B1 (ko) 1995-06-14
JPH04184785A (ja) 1992-07-01
KR920010624A (ko) 1992-06-26

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129