IT1255779B - Circuito di trasmissione di dati per una memoria ad accesso casuale dinamica - Google Patents

Circuito di trasmissione di dati per una memoria ad accesso casuale dinamica

Info

Publication number
IT1255779B
IT1255779B ITMI921989A ITMI921989A IT1255779B IT 1255779 B IT1255779 B IT 1255779B IT MI921989 A ITMI921989 A IT MI921989A IT MI921989 A ITMI921989 A IT MI921989A IT 1255779 B IT1255779 B IT 1255779B
Authority
IT
Italy
Prior art keywords
channel
pair
input
transistors
output
Prior art date
Application number
ITMI921989A
Other languages
English (en)
Italian (it)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from KR1019910014099A external-priority patent/KR940008294B1/ko
Priority claimed from KR1019910014098A external-priority patent/KR940004517B1/ko
Application filed filed Critical
Publication of ITMI921989A0 publication Critical patent/ITMI921989A0/it
Publication of ITMI921989A1 publication Critical patent/ITMI921989A1/it
Application granted granted Critical
Publication of IT1255779B publication Critical patent/IT1255779B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 

Landscapes

  • Engineering & Computer Science (AREA)
  • Databases & Information Systems (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Semiconductor Memories (AREA)
  • Static Random-Access Memory (AREA)
ITMI921989A 1991-08-14 1992-08-13 Circuito di trasmissione di dati per una memoria ad accesso casuale dinamica IT1255779B (it)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1019910014099A KR940008294B1 (ko) 1991-08-14 1991-08-14 공통 입출력선을 가지는 고속 데이타 전송회로
KR1019910014098A KR940004517B1 (ko) 1991-08-14 1991-08-14 공통 입출력선을 가지는 데이타 전송회로

Publications (3)

Publication Number Publication Date
ITMI921989A0 ITMI921989A0 (it) 1992-08-13
ITMI921989A1 ITMI921989A1 (it) 1994-02-13
IT1255779B true IT1255779B (it) 1995-11-15

Family

ID=26628708

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI921989A IT1255779B (it) 1991-08-14 1992-08-13 Circuito di trasmissione di dati per una memoria ad accesso casuale dinamica

Country Status (7)

Country Link
US (1) US5283760A (enExample)
JP (1) JP2661842B2 (enExample)
DE (1) DE4226844C2 (enExample)
FR (1) FR2680429B1 (enExample)
GB (1) GB2259384B (enExample)
IT (1) IT1255779B (enExample)
TW (1) TW245857B (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940007640B1 (ko) * 1991-07-31 1994-08-22 삼성전자 주식회사 공통 입출력선을 가지는 데이타 전송회로
KR950009234B1 (ko) * 1992-02-19 1995-08-18 삼성전자주식회사 반도체 메모리장치의 비트라인 분리클럭 발생장치
JP2663838B2 (ja) * 1993-07-27 1997-10-15 日本電気株式会社 半導体集積回路装置
US6044481A (en) * 1997-05-09 2000-03-28 Artisan Components, Inc. Programmable universal test interface for testing memories with different test methodologies
AU1119799A (en) * 1997-10-25 1999-05-17 Artisan Components, Inc. Low power differential signal transition techniques for use in memory devices
DE19828657C2 (de) * 1998-06-26 2001-01-04 Siemens Ag Integrierter Speicher
JP2000100172A (ja) * 1998-07-22 2000-04-07 Mitsubishi Electric Corp 半導体記憶装置
US6448631B2 (en) 1998-09-23 2002-09-10 Artisan Components, Inc. Cell architecture with local interconnect and method for making same
JP2000243086A (ja) 1998-12-24 2000-09-08 Mitsubishi Electric Corp 半導体記憶装置
US6367059B1 (en) 1999-03-23 2002-04-02 Artisan Components, Inc. Carry chain standard cell with charge sharing reduction architecture
US6222777B1 (en) * 1999-04-09 2001-04-24 Sun Microsystems, Inc. Output circuit for alternating multiple bit line per column memory architecture
JP4667594B2 (ja) * 2000-12-25 2011-04-13 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
KR100546308B1 (ko) * 2002-12-13 2006-01-26 삼성전자주식회사 데이터 독출 능력이 향상된 반도체 메모리 장치.
KR100763247B1 (ko) * 2006-05-25 2007-10-04 삼성전자주식회사 로컬 센스앰프를 갖는 반도체 메모리 장치

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60150296A (ja) * 1984-01-13 1985-08-07 Nec Corp スタテイツクメモリ回路
JPS6258492A (ja) * 1985-09-09 1987-03-14 Toshiba Corp 半導体記憶装置
KR890003488B1 (ko) * 1986-06-30 1989-09-22 삼성전자 주식회사 데이터 전송회로
JPH02246516A (ja) * 1989-03-20 1990-10-02 Hitachi Ltd 半導体装置
JPH02301097A (ja) * 1989-05-15 1990-12-13 Toshiba Corp ダイナミック型ランダムアクセスメモリ
JP3101297B2 (ja) * 1990-03-30 2000-10-23 株式会社東芝 半導体メモリ装置
JP3101298B2 (ja) * 1990-03-30 2000-10-23 株式会社東芝 半導体メモリ装置

Also Published As

Publication number Publication date
FR2680429B1 (fr) 1994-03-25
GB2259384A (en) 1993-03-10
JP2661842B2 (ja) 1997-10-08
JPH05205475A (ja) 1993-08-13
ITMI921989A0 (it) 1992-08-13
TW245857B (enExample) 1995-04-21
US5283760A (en) 1994-02-01
DE4226844C2 (de) 1994-12-01
DE4226844A1 (de) 1993-02-18
GB2259384B (en) 1995-12-20
GB9217373D0 (en) 1992-09-30
ITMI921989A1 (it) 1994-02-13
FR2680429A1 (fr) 1993-02-19

Similar Documents

Publication Publication Date Title
IT1255779B (it) Circuito di trasmissione di dati per una memoria ad accesso casuale dinamica
KR930001226A (ko) 고속 센싱 동작을 수행하는 센스 앰프
US5029136A (en) High-speed DRAM sense amp with high noise immunity
KR930003149A (ko) 공통 입출력선을 가지는 데이타 전송회로
KR900019019A (ko) 고밀도 반도체 메모리장치의 전원 공급전압 변환회로
TW344819B (en) Semiconductor memory device
KR890008826A (ko) 다이나믹 랜덤 액세스 메모리에 있어서의 센스앰프 구동장치 및 센스앰프 구동방법
KR900019038A (ko) 다이나믹형 랜덤억세스메모리
EP0821364B1 (en) Sense circuit
IT1252280B (it) Memoria a semiconduttore del tipo ad amplificatore sensore comune
IT1263771B (it) Circuito di emissione dati di un dispositivo di memoria a semiconduttore
KR870008320A (ko) 상이형 메모리셀로 구성되는 반도체 메모리장치
US4045785A (en) Sense amplifier for static memory device
KR970067366A (ko) 복수 비트 데이타를 기억하는 메모리 셀을 가진 디램
TW286404B (en) Semiconductor memory device for reducing operating power consumption amount
ES470267A1 (es) Un circuito perfeccionado de celda de memoria
KR970029861A (ko) 비휠발성 레지스터 및 이 비휘발성 레지스터의 데이타 액세스방법
US20020048207A1 (en) Data bus sense amplifier circuit
TW333650B (en) The semiconductor memory, device & signal magnifying method
KR950020734A (ko) 반도체 기억장치
JP2573887B2 (ja) ダイナミックランダムアクセスメモリ用分離回路
US5058073A (en) CMOS RAM having a complementary channel sense amplifier
KR900008523A (ko) 반도체 메모리 소자
KR940001149A (ko) 반도체 기억장치
JPH0689577A (ja) 半導体記憶装置

Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970826