IT1252280B - Memoria a semiconduttore del tipo ad amplificatore sensore comune - Google Patents

Memoria a semiconduttore del tipo ad amplificatore sensore comune

Info

Publication number
IT1252280B
IT1252280B ITMI913091A ITMI913091A IT1252280B IT 1252280 B IT1252280 B IT 1252280B IT MI913091 A ITMI913091 A IT MI913091A IT MI913091 A ITMI913091 A IT MI913091A IT 1252280 B IT1252280 B IT 1252280B
Authority
IT
Italy
Prior art keywords
memory cells
semiconductor memory
sensor amplifier
pair
transistors
Prior art date
Application number
ITMI913091A
Other languages
English (en)
Inventor
Yuto Ikeda
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI913091A0 publication Critical patent/ITMI913091A0/it
Publication of ITMI913091A1 publication Critical patent/ITMI913091A1/it
Application granted granted Critical
Publication of IT1252280B publication Critical patent/IT1252280B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Un dispositivo di memoria a semiconduttore comprende due matrici (1a, 1b) di celle di memoria. Le matrici (1a, 1b) di celle di memoria sono previste in comune con un gruppo di amplificatori sensori (2). Ciascun amplificatore sensore (20) di un gruppo di amplificatori sensori (2) è collegato ad una corrispondente coppia (BL1, BL1) di linee di bit entro una matrice (1a) di celle di memoria attraverso una coppia di transistor di trasmissione (S1, S3) formati da transistor MOS a canale N, e collegati ad una corrispondente coppia (BL2, BL2) di linee di bit entro l'altra matrice (1b) di celle di memoria attraverso una coppia di transistor di trasmissione (S2, 24) formata da transistor MOS a canale P. I medesimi segnali di controllo sono applicati a porte di queste coppie di transistor di trasmissione (S1 - S4). I segnali di controllo mantengono un livello 1/2 Vcc durante un periodo di precarica, e salgono a livelli alti o scendono a livelli bassi.
ITMI913091A 1990-11-21 1991-11-20 Memoria a semiconduttore del tipo ad amplificatore sensore comune IT1252280B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2318676A JPH04186593A (ja) 1990-11-21 1990-11-21 半導体記憶装置

Publications (3)

Publication Number Publication Date
ITMI913091A0 ITMI913091A0 (it) 1991-11-20
ITMI913091A1 ITMI913091A1 (it) 1993-05-20
IT1252280B true IT1252280B (it) 1995-06-08

Family

ID=18101786

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI913091A IT1252280B (it) 1990-11-21 1991-11-20 Memoria a semiconduttore del tipo ad amplificatore sensore comune

Country Status (5)

Country Link
US (1) US5243574A (it)
JP (1) JPH04186593A (it)
KR (1) KR950001289B1 (it)
DE (1) DE4138340C2 (it)
IT (1) IT1252280B (it)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3319610B2 (ja) * 1991-11-22 2002-09-03 日本テキサス・インスツルメンツ株式会社 信号伝達回路
KR970004460B1 (ko) * 1992-06-30 1997-03-27 니뽄 덴끼 가부시끼가이샤 반도체 메모리 회로
JP2814846B2 (ja) * 1992-07-29 1998-10-27 日本電気株式会社 半導体記憶装置
JPH0757466A (ja) * 1993-08-12 1995-03-03 Toshiba Corp 半導体集積回路
JPH07326192A (ja) * 1994-05-31 1995-12-12 Toshiba Micro Comput Eng Corp 半導体記憶装置
US5907516A (en) * 1994-07-07 1999-05-25 Hyundai Electronics Industries Co., Ltd. Semiconductor memory device with reduced data bus line load
US5836007A (en) * 1995-09-14 1998-11-10 International Business Machines Corporation Methods and systems for improving memory component size and access speed including splitting bit lines and alternate pre-charge/access cycles
US5561630A (en) * 1995-09-28 1996-10-01 International Business Machines Coporation Data sense circuit for dynamic random access memories
US5710738A (en) * 1996-12-17 1998-01-20 Powerchip Semiconductor Corp. Low power dynamic random access memory
JPH10302469A (ja) * 1997-04-25 1998-11-13 Fujitsu Ltd 半導体記憶装置
KR100297727B1 (ko) * 1998-08-13 2001-09-26 윤종용 분리 제어라인의 큰 부하에 의한 스피드 손실을 방지할 수 있는반도체 메모리 장치
KR100395877B1 (ko) * 2000-11-10 2003-08-25 삼성전자주식회사 반도체 메모리의 데이타 감지 장치
KR100382614B1 (ko) * 2000-12-29 2003-05-09 주식회사 하이닉스반도체 저전력의 메모리 코아 제어 장치
US6580655B2 (en) * 2001-08-29 2003-06-17 International Business Machines Corporation Pre-charge circuit and method for memory devices with shared sense amplifiers
JP4462528B2 (ja) 2002-06-24 2010-05-12 株式会社日立製作所 半導体集積回路装置
KR100838363B1 (ko) 2005-10-20 2008-06-13 주식회사 하이닉스반도체 센스앰프 회로
KR100871083B1 (ko) * 2007-02-27 2008-11-28 삼성전자주식회사 입출력 센스앰프를 구비하는 반도체 메모리 장치의레이아웃 구조
US8050127B2 (en) * 2009-02-06 2011-11-01 Hynix Semiconductor Inc. Semiconductor memory device
US8437204B2 (en) * 2009-06-12 2013-05-07 Taiwan Semiconductor Manufacturing Company, Ltd. Memory array with corresponding row and column control signals
KR101033490B1 (ko) * 2009-11-30 2011-05-09 주식회사 하이닉스반도체 패드를 선택적으로 이용하는 반도체 메모리 장치

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62273694A (ja) * 1986-05-22 1987-11-27 Sony Corp センスアンプ
JPS632197A (ja) * 1986-06-20 1988-01-07 Mitsubishi Electric Corp 半導体記憶装置
JP2644261B2 (ja) * 1988-03-15 1997-08-25 株式会社東芝 ダイナミック型半導体記憶装置
JPH0229989A (ja) * 1988-07-19 1990-01-31 Mitsubishi Electric Corp ダイナミックランダムアクセスメモリ装置
JPH0713861B2 (ja) * 1988-12-05 1995-02-15 三菱電機株式会社 半導体記憶装置

Also Published As

Publication number Publication date
JPH04186593A (ja) 1992-07-03
US5243574A (en) 1993-09-07
KR950001289B1 (ko) 1995-02-15
DE4138340C2 (de) 1994-01-20
DE4138340A1 (de) 1992-05-27
ITMI913091A1 (it) 1993-05-20
KR920010638A (ko) 1992-06-26
ITMI913091A0 (it) 1991-11-20

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Legal Events

Date Code Title Description
0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129