IT1246231B - Dispositivo a semiconduttore avente uno strato di blocco del canale doppiamente drogato e suo metodo di fabbricazione - Google Patents

Dispositivo a semiconduttore avente uno strato di blocco del canale doppiamente drogato e suo metodo di fabbricazione

Info

Publication number
IT1246231B
IT1246231B ITMI910106A ITMI910106A IT1246231B IT 1246231 B IT1246231 B IT 1246231B IT MI910106 A ITMI910106 A IT MI910106A IT MI910106 A ITMI910106 A IT MI910106A IT 1246231 B IT1246231 B IT 1246231B
Authority
IT
Italy
Prior art keywords
impurity
manufacturing
substrate
semiconductor device
layer
Prior art date
Application number
ITMI910106A
Other languages
English (en)
Inventor
Yun-Seung Sin
Kyung-Tae Kim
Jun Kang
Original Assignee
Samsung Electronics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Samsung Electronics Co Ltd filed Critical Samsung Electronics Co Ltd
Publication of ITMI910106A0 publication Critical patent/ITMI910106A0/it
Publication of ITMI910106A1 publication Critical patent/ITMI910106A1/it
Application granted granted Critical
Publication of IT1246231B publication Critical patent/IT1246231B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0925—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising an N-well only in the substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)

Abstract

Dispositivo a semiconduttore comprende: una regione di isolamento, per definire una regione attiva e una regione di contatto con il substrato su un substrato semiconduttore drogato con una prima impurezza; un primo strato di blocco del canale formato drogando con prima impurezza avente una densità maggiore di quella della prima impurezza del substrato, su una porzione del substrato contattante la superficie inferiore dello strato di ossido di campo, un secondo strato di blocco del canale formato drogando con prima impurezza avente una densità maggiore di quella della prima impurezza del primo strato di blocco del canale, su una porzione del substrato spaziata orizzontalmente a una distanza prescritta dalla regione attiva e contattando la superficie inferiore dello strato di ossido di campo. Metodo per fabbricare il dispositivo comprendente la fabbricazione di uno strato di blocco del canale doppiamente drogato. Può essere evitato il malfunzionamento dovuto a portatori caldi e può essere aumentata la tolleranza al latchup diminuendo la resistenza di massa.
ITMI910106A 1990-10-05 1991-01-18 Dispositivo a semiconduttore avente uno strato di blocco del canale doppiamente drogato e suo metodo di fabbricazione IT1246231B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019900015802A KR920008951A (ko) 1990-10-05 1990-10-05 더블도우프된 채널스톱층을 가지는 반도체장치 및 그 제조방법

Publications (3)

Publication Number Publication Date
ITMI910106A0 ITMI910106A0 (it) 1991-01-18
ITMI910106A1 ITMI910106A1 (it) 1992-07-18
IT1246231B true IT1246231B (it) 1994-11-16

Family

ID=19304337

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI910106A IT1246231B (it) 1990-10-05 1991-01-18 Dispositivo a semiconduttore avente uno strato di blocco del canale doppiamente drogato e suo metodo di fabbricazione

Country Status (6)

Country Link
JP (1) JPH04234161A (it)
KR (1) KR920008951A (it)
DE (1) DE4101313A1 (it)
FR (1) FR2667726A1 (it)
GB (1) GB2248516A (it)
IT (1) IT1246231B (it)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR0170285B1 (ko) * 1995-05-12 1999-03-30 김광호 반도체 장치의 소자 분리 방법
KR100685359B1 (ko) * 2002-09-09 2007-02-22 산요덴키가부시키가이샤 보호 소자
KR101106988B1 (ko) * 2010-07-22 2012-01-25 윤지윤 대걸레

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4268847A (en) * 1977-09-16 1981-05-19 Nippon Electric Co., Ltd. Semiconductor device having an insulated gate type field effect transistor and method for producing the same
US4458262A (en) * 1980-05-27 1984-07-03 Supertex, Inc. CMOS Device with ion-implanted channel-stop region and fabrication method therefor
US4411058A (en) * 1981-08-31 1983-10-25 Hughes Aircraft Company Process for fabricating CMOS devices with self-aligned channel stops
JPS5837946A (ja) * 1981-08-31 1983-03-05 Fujitsu Ltd Ｍｉｓ型半導体集積回路装置
EP0179088B1 (en) * 1984-03-29 1988-08-24 Hughes Aircraft Company A latch-up resistant cmos structure for vlsi
JPS61111576A (ja) * 1984-10-13 1986-05-29 Fujitsu Ltd 半導体装置
JPS61207052A (ja) * 1985-03-12 1986-09-13 Sanyo Electric Co Ltd 高耐圧ｃｍｏｓ半導体装置
US4829019A (en) * 1987-05-12 1989-05-09 Texas Instruments Incorporated Method for increasing source/drain to channel stop breakdown and decrease P+/N+ encroachment
JP2772020B2 (ja) * 1989-02-22 1998-07-02 株式会社東芝 Ｍｏｓ型半導体装置
JPH0766946B2 (ja) * 1989-03-31 1995-07-19 株式会社東芝 半導体装置及びその製造方法

Also Published As

Publication number Publication date
GB2248516A (en) 1992-04-08
JPH04234161A (ja) 1992-08-21
FR2667726A1 (fr) 1992-04-10
DE4101313A1 (de) 1992-04-09
GB9100618D0 (en) 1991-02-27
KR920008951A (ko) 1992-05-28
ITMI910106A1 (it) 1992-07-18
ITMI910106A0 (it) 1991-01-18

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Legal Events

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TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19970522