IT1171797B - Strati di silicio policristallino per dispositivo semiconduttori - Google Patents

Strati di silicio policristallino per dispositivo semiconduttori

Info

Publication number
IT1171797B
IT1171797B IT23690/83A IT2369083A IT1171797B IT 1171797 B IT1171797 B IT 1171797B IT 23690/83 A IT23690/83 A IT 23690/83A IT 2369083 A IT2369083 A IT 2369083A IT 1171797 B IT1171797 B IT 1171797B
Authority
IT
Italy
Prior art keywords
semiconductor devices
polycrystalline silicon
silicon layers
layers
polycrystalline
Prior art date
Application number
IT23690/83A
Other languages
English (en)
Other versions
IT8323690A0 (it
Inventor
Alois Erhard Widmer
Guenther Harbeke
Liselotte Krausbauer
Edgar Felix Steigmeier
Original Assignee
Rca Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rca Corp filed Critical Rca Corp
Publication of IT8323690A0 publication Critical patent/IT8323690A0/it
Application granted granted Critical
Publication of IT1171797B publication Critical patent/IT1171797B/it

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/32055—Deposition of semiconductive layers, e.g. poly - or amorphous silicon layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Photovoltaic Devices (AREA)
  • Chemical Vapour Deposition (AREA)
IT23690/83A 1982-11-12 1983-11-11 Strati di silicio policristallino per dispositivo semiconduttori IT1171797B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US44137182A 1982-11-12 1982-11-12

Publications (2)

Publication Number Publication Date
IT8323690A0 IT8323690A0 (it) 1983-11-11
IT1171797B true IT1171797B (it) 1987-06-10

Family

ID=23752618

Family Applications (1)

Application Number Title Priority Date Filing Date
IT23690/83A IT1171797B (it) 1982-11-12 1983-11-11 Strati di silicio policristallino per dispositivo semiconduttori

Country Status (6)

Country Link
JP (1) JPH0652715B2 (it)
DE (1) DE3340584A1 (it)
FR (1) FR2536210B1 (it)
GB (1) GB2130009B (it)
IT (1) IT1171797B (it)
SE (1) SE500463C2 (it)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4504521A (en) * 1984-03-22 1985-03-12 Rca Corporation LPCVD Deposition of tantalum silicide
GB8504725D0 (en) * 1985-02-23 1985-03-27 Standard Telephones Cables Ltd Integrated circuits
US4789883A (en) * 1985-12-17 1988-12-06 Advanced Micro Devices, Inc. Integrated circuit structure having gate electrode and underlying oxide and method of making same
EP0253014B1 (en) * 1986-07-18 1990-04-11 Nippondenso Co., Ltd. Method of manufacturing a monvolatile semiconductor memory apparatus with writing and erasing capability
GB2204066A (en) * 1987-04-06 1988-11-02 Philips Electronic Associated A method for manufacturing a semiconductor device having a layered structure
JP2690917B2 (ja) * 1987-12-07 1997-12-17 株式会社日立製作所 薄膜形成方法及び半導体装置の製造方法
FR2627012B1 (fr) * 1988-02-10 1990-06-01 France Etat Procede de depot d'une couche polycristalline a gros grains, couche obtenue et transistor pourvu d'une telle couche
EP0429885B1 (en) * 1989-12-01 1997-06-04 Texas Instruments Incorporated Method of in-situ doping of deposited silicon
US5366917A (en) * 1990-03-20 1994-11-22 Nec Corporation Method for fabricating polycrystalline silicon having micro roughness on the surface
JP2508948B2 (ja) * 1991-06-21 1996-06-19 日本電気株式会社 半導体装置の製造方法
GB2293691B (en) * 1991-09-07 1996-06-19 Samsung Electronics Co Ltd Semiconductor memory devices
KR960026821A (ko) * 1994-12-20 1996-07-22 김주용 캐패시터 제조방법
KR100295718B1 (ko) * 1995-06-06 2001-09-03 아사히 가세이 마이크로시스템 가부시끼가이샤 반도체장치및그의제조방법
US5733641A (en) * 1996-05-31 1998-03-31 Xerox Corporation Buffered substrate for semiconductor devices
US6970644B2 (en) 2000-12-21 2005-11-29 Mattson Technology, Inc. Heating configuration for use in thermal processing chambers
US7015422B2 (en) 2000-12-21 2006-03-21 Mattson Technology, Inc. System and process for heating semiconductor wafers by optimizing absorption of electromagnetic energy

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS558815B2 (it) * 1973-06-29 1980-03-06
DE2536174C3 (de) * 1975-08-13 1983-11-03 Siemens AG, 1000 Berlin und 8000 München Verfahren zum Herstellen von polykristallinen Siliciumschichten für Halbleiterbauelemente
JPS5249782A (en) * 1975-10-20 1977-04-21 Fujitsu Ltd Process for production of semiconductor device
US4179528A (en) * 1977-05-18 1979-12-18 Eastman Kodak Company Method of making silicon device with uniformly thick polysilicon
FR2394173A1 (fr) * 1977-06-06 1979-01-05 Thomson Csf Procede de fabrication de dispositifs electroniques qui comportent une couche mince de silicium amorphe et dispositif electronique obtenu par un tel procede
JPS5423386A (en) * 1977-07-22 1979-02-21 Hitachi Ltd Manufacture of semiconductor device
JPS5617083A (en) * 1979-07-20 1981-02-18 Hitachi Ltd Semiconductor device and its manufacture
US4358326A (en) * 1980-11-03 1982-11-09 International Business Machines Corporation Epitaxially extended polycrystalline structures utilizing a predeposit of amorphous silicon with subsequent annealing
US4441249A (en) * 1982-05-26 1984-04-10 Bell Telephone Laboratories, Incorporated Semiconductor integrated circuit capacitor

Also Published As

Publication number Publication date
FR2536210A1 (fr) 1984-05-18
IT8323690A0 (it) 1983-11-11
SE500463C2 (sv) 1994-06-27
GB8329381D0 (en) 1983-12-07
JPH0652715B2 (ja) 1994-07-06
DE3340584A1 (de) 1984-05-17
GB2130009A (en) 1984-05-23
FR2536210B1 (fr) 1986-03-28
GB2130009B (en) 1986-04-03
SE8306070D0 (sv) 1983-11-04
SE8306070L (sv) 1984-05-13
JPS59100561A (ja) 1984-06-09
DE3340584C2 (it) 1993-02-11

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Legal Events

Date Code Title Description
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971125