HK212496A - Storage cell arrangement and process for operating it - Google Patents

Storage cell arrangement and process for operating it

Info

Publication number
HK212496A
HK212496A HK212496A HK212496A HK212496A HK 212496 A HK212496 A HK 212496A HK 212496 A HK212496 A HK 212496A HK 212496 A HK212496 A HK 212496A HK 212496 A HK212496 A HK 212496A
Authority
HK
Hong Kong
Prior art keywords
pct
effect transistor
field
ferroelectric layer
cell arrangement
Prior art date
Application number
HK212496A
Other languages
English (en)
Inventor
Wolfgang Dr Krautschneider
Wolfram Dipl Phys Wersing
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of HK212496A publication Critical patent/HK212496A/xx

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/516—Insulating materials associated therewith with at least one ferroelectric layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
  • Hybrid Cells (AREA)
  • Dram (AREA)
  • Medicines Containing Material From Animals Or Micro-Organisms (AREA)
HK212496A 1991-01-09 1996-12-05 Storage cell arrangement and process for operating it HK212496A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4100465 1991-01-09

Publications (1)

Publication Number Publication Date
HK212496A true HK212496A (en) 1996-12-06

Family

ID=6422741

Family Applications (1)

Application Number Title Priority Date Filing Date
HK212496A HK212496A (en) 1991-01-09 1996-12-05 Storage cell arrangement and process for operating it

Country Status (9)

Country Link
US (1) US5471417A (xx)
EP (1) EP0566585B1 (xx)
JP (1) JP3307928B2 (xx)
KR (1) KR100229961B1 (xx)
AT (1) ATE120579T1 (xx)
DE (1) DE59105063D1 (xx)
HK (1) HK212496A (xx)
TW (1) TW231377B (xx)
WO (1) WO1992012518A1 (xx)

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JP3805001B2 (ja) * 1995-06-08 2006-08-02 株式会社ルネサステクノロジ 半導体装置
US5789775A (en) * 1996-01-26 1998-08-04 Radiant Technologies High density memory and double word ferroelectric memory cell for constructing the same
KR100403798B1 (ko) * 1996-03-11 2004-06-26 삼성전자주식회사 겹침형강유전체랜덤액세서메모리및그제조방법과구동방법
US5877977A (en) * 1996-09-10 1999-03-02 National Semiconductor Corporation Nonvolatile memory based on metal-ferroelectric-metal-insulator semiconductor structure
DE19720193C2 (de) * 1997-05-14 2002-10-17 Infineon Technologies Ag Integrierte Schaltungsanordnung mit mindestens zwei vertikalen MOS-Transistoren und Verfahren zu deren Herstellung
DE19850852A1 (de) 1998-11-04 2000-05-11 Siemens Ag Ferroelektrischer Transistor und Verfahren zu dessen Herstellung
DE19926767A1 (de) * 1999-06-11 2000-12-21 Infineon Technologies Ag Ferroelektrischer Transistor und Verfahren zu dessen Herstellung
DE19931125A1 (de) * 1999-07-06 2001-01-25 Infineon Technologies Ag Ferroelektrischer Transistor
DE19931124C1 (de) * 1999-07-06 2001-02-15 Infineon Technologies Ag Speicherzellenanordnung mit einem ferroelektrischen Transistor
DE19946437A1 (de) * 1999-09-28 2001-04-12 Infineon Technologies Ag Ferroelektrischer Transistor
DE19947117B4 (de) * 1999-09-30 2007-03-08 Infineon Technologies Ag Ferroelektrischer Transistor und dessen Verwendung in einer Speicherzellenanordnung
TW502255B (en) * 2000-02-14 2002-09-11 Infineon Technologies Ag Method for reading and storing a state from or in a ferroelectric transistor in a memory cell, and a memory matrix
JP3627640B2 (ja) 2000-09-22 2005-03-09 松下電器産業株式会社 半導体メモリ素子
DE10156470B4 (de) * 2001-11-16 2006-06-08 Infineon Technologies Ag RF-ID-Etikett mit einer Halbleiteranordnung mit Transistoren auf Basis organischer Halbleiter und nichtflüchtiger Schreib-Lese-Speicherzellen
DE10200475A1 (de) * 2002-01-09 2003-07-24 Samsung Sdi Co Nichtflüchtiges Speicherelement und Anzeigematrizen daraus
KR100626912B1 (ko) * 2004-04-23 2006-09-20 주식회사 하이닉스반도체 불휘발성 강유전체 수직 전극 셀과 수직 전극 셀을 이용한불휘발성 강유전체 메모리 장치 및 그 수직 전극 셀 제조방법
DE102005017072A1 (de) * 2004-12-29 2006-07-13 Hynix Semiconductor Inc., Ichon Ladungsfalle- bzw. Ladung-Trap-Isolator-Speichereinrichtung
KR100696766B1 (ko) * 2004-12-29 2007-03-19 주식회사 하이닉스반도체 차지 트랩 인슐레이터 메모리 장치
JP2007258613A (ja) * 2006-03-24 2007-10-04 Toshiba Corp 強誘電体記憶装置およびその製造方法
US8335100B2 (en) * 2007-06-14 2012-12-18 Micron Technology, Inc. Circuit, biasing scheme and fabrication method for diode accessed cross-point resistive memory array
US9041082B2 (en) 2010-10-07 2015-05-26 International Business Machines Corporation Engineering multiple threshold voltages in an integrated circuit
US8796751B2 (en) 2012-11-20 2014-08-05 Micron Technology, Inc. Transistors, memory cells and semiconductor constructions
KR102598993B1 (ko) * 2021-11-11 2023-11-07 한국생산기술연구원 불감층 효과가 개선된 강유전체 전계효과 트랜지스터 및 이의 제조방법
KR20230161705A (ko) 2022-05-19 2023-11-28 에스케이매직 주식회사 필터 살균 장치 및 이를 구비하는 공기청정기

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD160601A3 (de) * 1981-05-18 1983-11-16 Albrecht Moeschwitzer Halbleiterspeicherelement mit 2 feldeffekttransistoren
US4427989A (en) * 1981-08-14 1984-01-24 International Business Machines Corporation High density memory cell
US4488265A (en) * 1982-06-30 1984-12-11 Ibm Corporation Integrated dynamic RAM and ROS
JPS6013398A (ja) * 1983-07-04 1985-01-23 Hitachi Ltd 半導体多値記憶装置
US4829351A (en) * 1987-03-16 1989-05-09 Motorola, Inc. Polysilicon pattern for a floating gate memory
JPH0687500B2 (ja) * 1987-03-26 1994-11-02 日本電気株式会社 半導体記憶装置およびその製造方法
US5198994A (en) * 1988-08-31 1993-03-30 Kabushiki Kaisha Toshiba Ferroelectric memory device
KR940011483B1 (ko) * 1990-11-28 1994-12-19 가부시끼가이샤 도시바 반도체 디바이스를 제조하기 위한 방법 및 이 방법에 의해 제조되는 반도체 디바이스

Also Published As

Publication number Publication date
JP3307928B2 (ja) 2002-07-29
KR100229961B1 (ko) 1999-11-15
EP0566585A1 (de) 1993-10-27
TW231377B (xx) 1994-10-01
DE59105063D1 (de) 1995-05-04
JPH06504409A (ja) 1994-05-19
ATE120579T1 (de) 1995-04-15
EP0566585B1 (de) 1995-03-29
KR930703683A (ko) 1993-11-30
US5471417A (en) 1995-11-28
WO1992012518A1 (de) 1992-07-23

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Legal Events

Date Code Title Description
PC Patent ceased (i.e. patent has lapsed due to the failure to pay the renewal fee)