HK1202658A1 - 電子裝置 - Google Patents

電子裝置

Info

Publication number
HK1202658A1
HK1202658A1 HK15102860.6A HK15102860A HK1202658A1 HK 1202658 A1 HK1202658 A1 HK 1202658A1 HK 15102860 A HK15102860 A HK 15102860A HK 1202658 A1 HK1202658 A1 HK 1202658A1
Authority
HK
Hong Kong
Prior art keywords
electronic device
electronic
Prior art date
Application number
HK15102860.6A
Other languages
English (en)
Inventor
Toru Hayashi
Motoo Suwa
Original Assignee
Renesas Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Electronics Corp filed Critical Renesas Electronics Corp
Publication of HK1202658A1 publication Critical patent/HK1202658A1/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076—Timing circuits
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Databases & Information Systems (AREA)
  • Dram (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Memory System (AREA)
HK15102860.6A 2013-08-09 2015-03-20 電子裝置 HK1202658A1 (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013166537A JP6200236B2 (ja) 2013-08-09 2013-08-09 電子装置

Publications (1)

Publication Number Publication Date
HK1202658A1 true HK1202658A1 (zh) 2015-10-02

Family

ID=52448554

Family Applications (1)

Application Number Title Priority Date Filing Date
HK15102860.6A HK1202658A1 (zh) 2013-08-09 2015-03-20 電子裝置

Country Status (4)

Country Link
US (3) US9704559B2 (zh)
JP (1) JP6200236B2 (zh)
CN (1) CN104346281B (zh)
HK (1) HK1202658A1 (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6434870B2 (ja) * 2015-07-28 2018-12-05 ルネサスエレクトロニクス株式会社 電子装置
JP6543129B2 (ja) * 2015-07-29 2019-07-10 ルネサスエレクトロニクス株式会社 電子装置
JP2017163204A (ja) * 2016-03-07 2017-09-14 ＡＰＲＥＳＩＡ Ｓｙｓｔｅｍｓ株式会社 通信装置
KR20190087893A (ko) * 2018-01-17 2019-07-25 삼성전자주식회사 클럭을 공유하는 반도체 패키지 및 전자 시스템
KR102567974B1 (ko) 2018-05-30 2023-08-17 삼성전자주식회사 인쇄회로기판을 포함하는 메모리 시스템 및 스토리지 장치
KR102605145B1 (ko) 2018-07-13 2023-11-24 에스케이하이닉스 주식회사 복수의 채널로 동작하는 복수의 다이를 포함하는 반도체 장치
US10685948B1 (en) 2018-11-29 2020-06-16 Apple Inc. Double side mounted large MCM package with memory channel length reduction
TWI681695B (zh) * 2019-01-31 2020-01-01 瑞昱半導體股份有限公司 可避免搭配運作的記憶體晶片效能降級的信號處理電路
CN111508942B (zh) * 2019-01-31 2022-02-25 瑞昱半导体股份有限公司 可避免搭配运行的存储器芯片效能降级的信号处理电路
DE112019007422T5 (de) 2019-05-31 2022-02-24 Micron Technology, Inc. Speicherkomponente für ein system-on-chip-gerät
US11367478B2 (en) * 2020-01-14 2022-06-21 Changxin Memory Technologies, Inc. Integrated circuit structure and memory
JP7324155B2 (ja) 2020-01-27 2023-08-09 ルネサスエレクトロニクス株式会社 半導体装置
TWI795644B (zh) * 2020-06-02 2023-03-11 大陸商上海兆芯集成電路有限公司 電子總成
KR20220066445A (ko) 2020-11-16 2022-05-24 삼성전자주식회사 모듈 보드 및 이를 포함하는 메모리 모듈
US20240006387A1 (en) * 2022-07-01 2024-01-04 Gm Cruise Holdings Llc Printed circuit board with single rank memory configuration using partially aligned memory circuits

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JP3634603B2 (ja) * 1997-12-02 2005-03-30 株式会社ルネサステクノロジ 信号伝送回路
JP4569913B2 (ja) * 2000-03-10 2010-10-27 エルピーダメモリ株式会社 メモリモジュール
JP2001265708A (ja) * 2000-03-16 2001-09-28 Toshiba Corp 電子機器及び電子機器の基板
JP2003008423A (ja) * 2001-06-22 2003-01-10 Mitsubishi Electric Corp バスインターフェイス回路
JP3821678B2 (ja) 2001-09-06 2006-09-13 エルピーダメモリ株式会社 メモリ装置
JP2003197753A (ja) 2001-12-26 2003-07-11 Elpida Memory Inc メモリ装置及びメモリバス伝送システム
JP3742051B2 (ja) * 2002-10-31 2006-02-01 エルピーダメモリ株式会社 メモリモジュール、メモリチップ、及びメモリシステム
DE10305837B4 (de) * 2003-02-12 2009-03-19 Qimonda Ag Speichermodul mit einer Mehrzahl von integrierten Speicherbauelementen
JP4205553B2 (ja) * 2003-11-06 2009-01-07 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
KR100933452B1 (ko) * 2003-11-19 2009-12-23 엘지디스플레이 주식회사 액정표시장치의 구동장치 및 구동방법
JP3896112B2 (ja) * 2003-12-25 2007-03-22 エルピーダメモリ株式会社 半導体集積回路装置
JP4647243B2 (ja) * 2004-05-24 2011-03-09 ルネサスエレクトロニクス株式会社 半導体装置
JP4152363B2 (ja) * 2004-08-13 2008-09-17 エルピーダメモリ株式会社 メモリ装置及びメモリバス伝送システム
US7331010B2 (en) * 2004-10-29 2008-02-12 International Business Machines Corporation System, method and storage medium for providing fault detection and correction in a memory subsystem
JP2006237365A (ja) 2005-02-25 2006-09-07 Agilent Technol Inc 半導体特性評価装置の管理方法及びそのプログラム
JP4674850B2 (ja) * 2005-02-25 2011-04-20 ルネサスエレクトロニクス株式会社 半導体装置
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JP5197080B2 (ja) 2008-03-19 2013-05-15 ルネサスエレクトロニクス株式会社 半導体装置及びデータプロセッサ
JP5669175B2 (ja) 2010-06-28 2015-02-12 ルネサスエレクトロニクス株式会社 電子機器
JP2012203807A (ja) * 2011-03-28 2012-10-22 Elpida Memory Inc メモリモジュール
JP2013114416A (ja) * 2011-11-28 2013-06-10 Elpida Memory Inc メモリモジュール
JP2013114415A (ja) * 2011-11-28 2013-06-10 Elpida Memory Inc メモリモジュール

Also Published As

Publication number Publication date
JP6200236B2 (ja) 2017-09-20
US20180012645A1 (en) 2018-01-11
US9704559B2 (en) 2017-07-11
CN104346281A (zh) 2015-02-11
JP2015035159A (ja) 2015-02-19
US20170243630A1 (en) 2017-08-24
US20150043298A1 (en) 2015-02-12
US9805785B2 (en) 2017-10-31
CN104346281B (zh) 2019-04-09
US9997231B2 (en) 2018-06-12

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