GB1372216A - Semiconductor device manufacture - Google Patents

Semiconductor device manufacture

Info

Publication number
GB1372216A
GB1372216A GB5793971A GB5793971A GB1372216A GB 1372216 A GB1372216 A GB 1372216A GB 5793971 A GB5793971 A GB 5793971A GB 5793971 A GB5793971 A GB 5793971A GB 1372216 A GB1372216 A GB 1372216A
Authority
GB
United Kingdom
Prior art keywords
frame
lead
lead frame
semi
leads
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5793971A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Philips Electronics UK Ltd
Original Assignee
Philips Electronic and Associated Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Electronic and Associated Industries Ltd filed Critical Philips Electronic and Associated Industries Ltd
Publication of GB1372216A publication Critical patent/GB1372216A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/04—Manufacture or treatment of leadframes
    • H10W70/048—Mechanical treatments, e.g. punching, cutting, deforming or cold welding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/40—Leadframes
    • H10W70/421—Shapes or dispositions
    • H10W70/424—Cross-sectional shapes
    • H10W70/427—Bent parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49121—Beam lead frame or beam lead device

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Wire Bonding (AREA)
GB5793971A 1970-12-17 1971-12-14 Semiconductor device manufacture Expired GB1372216A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL7018378A NL7018378A (enExample) 1970-12-17 1970-12-17

Publications (1)

Publication Number Publication Date
GB1372216A true GB1372216A (en) 1974-10-30

Family

ID=19811818

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5793971A Expired GB1372216A (en) 1970-12-17 1971-12-14 Semiconductor device manufacture

Country Status (8)

Country Link
US (1) US3842492A (enExample)
JP (1) JPS5135349B1 (enExample)
CA (1) CA933673A (enExample)
DE (1) DE2159530C3 (enExample)
FR (1) FR2118154B1 (enExample)
GB (1) GB1372216A (enExample)
IT (1) IT943262B (enExample)
NL (1) NL7018378A (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2323474A (en) * 1997-03-21 1998-09-23 Rohm Co Ltd A leadframe for a semiconductor device

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2259133C3 (de) * 1972-12-02 1982-03-11 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Verfahren zum Kontaktieren einer Halbleiteranordnung und Anwendung des Verfahrens
JPS5521128A (en) * 1978-08-02 1980-02-15 Hitachi Ltd Lead frame used for semiconductor device and its assembling
DE3040676A1 (de) * 1980-10-29 1982-05-27 Philips Patentverwaltung Gmbh, 2000 Hamburg Verfahren zum herstellen von halbleiteranordnugen
FR2498377A1 (fr) * 1981-01-16 1982-07-23 Thomson Csf Mat Tel Procede de fabrication de dispositifs semiconducteurs sur bande metallique
US4380042A (en) * 1981-02-23 1983-04-12 Angelucci Sr Thomas L Printed circuit lead carrier tape
JPS5817649A (ja) * 1981-07-24 1983-02-01 Fujitsu Ltd 電子部品パツケ−ジ
DE3378092D1 (en) * 1982-03-08 1988-10-27 Motorola Inc Integrated circuit lead frame
JPS58154241A (ja) * 1982-03-10 1983-09-13 Hitachi Ltd 半導体装置及びその製法
JPS59147448A (ja) * 1983-02-12 1984-08-23 Fujitsu Ltd 半導体素子搭載用リ−ドフレ−ムおよびこれを用いて製造される半導体装置とその製造方法
US4603927A (en) * 1984-07-12 1986-08-05 Rogers Corporation Surface mounted bussing device
JPS6132452A (ja) * 1984-07-25 1986-02-15 Hitachi Ltd リ−ドフレ−ムとそれを用いた電子装置
DE3430849A1 (de) * 1984-08-22 1986-03-06 Gerd 7742 St Georgen Kammerer Verfahren zur raeumlichen ausweitung der elektrischen verbindung zwischen den anschlusskontakten hochintegrierter elektronischer bauelemente und den kontaktstellen einer elektrischen anschlussvorrichtung auf einem bauelementetraeger
JPS61192542A (ja) * 1985-02-21 1986-08-27 Nifco Inc 溶着方法
JPS6281738A (ja) * 1985-10-07 1987-04-15 Hitachi Micro Comput Eng Ltd リ−ドフレ−ムおよびそれを用いた半導体装置
EP0242962A1 (en) * 1986-04-25 1987-10-28 Inmos Corporation Offset pad semiconductor lead frame
US5466967A (en) * 1988-10-10 1995-11-14 Lsi Logic Products Gmbh Lead frame for a multiplicity of terminals
US4916519A (en) * 1989-05-30 1990-04-10 International Business Machines Corporation Semiconductor package
US5781682A (en) * 1996-02-01 1998-07-14 International Business Machines Corporation Low-cost packaging for parallel optical computer link
JP6437406B2 (ja) * 2015-09-15 2018-12-12 東芝メモリ株式会社 半導体装置の製造方法、半導体装置、およびリードフレーム
JP2017168703A (ja) * 2016-03-17 2017-09-21 東芝メモリ株式会社 半導体装置の製造方法および半導体装置

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3262022A (en) * 1964-02-13 1966-07-19 Gen Micro Electronics Inc Packaged electronic device
US3391426A (en) * 1965-10-22 1968-07-09 Motorola Inc Molding apparatus
US3482419A (en) * 1966-01-03 1969-12-09 Texas Instruments Inc Process for fabricating hermetic glass seals
GB1173506A (en) * 1966-03-16 1969-12-10 Motorola Inc Metallic Frame Member for Fabrication of Semiconductor Devices.
DE1539692A1 (de) * 1966-06-23 1969-10-16 Blume & Redecker Gmbh Umklebevorrichtung fuer Spulen
DE1564867C3 (de) * 1966-06-30 1975-04-10 Telefunken Patentverwertungsgesellschaft Mbh, 7900 Ulm Verfahren zum Kontaktieren von Dioden, Planartransistoren und integrierten Schaltungen
FR1504726A (fr) * 1966-10-25 1967-12-08 Radiotechnique Coprim Rtc Perfectionnements aux procédés de fabrication de boîtiers pour dispositifs semiconducteurs
US3702954A (en) * 1967-07-21 1972-11-14 Siemens Ag Semiconductor component and method of its production
US3689336A (en) * 1971-01-04 1972-09-05 Sylvania Electric Prod Fabrication of packages for integrated circuits

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2323474A (en) * 1997-03-21 1998-09-23 Rohm Co Ltd A leadframe for a semiconductor device
US6107676A (en) * 1997-03-21 2000-08-22 Rohm Co., Ltd. Leadframe and a method of manufacturing a semiconductor device by use of it
GB2323474B (en) * 1997-03-21 2002-07-31 Rohm Co Ltd A leadframe and a method of manufacturing a semiconductor device device by use of it

Also Published As

Publication number Publication date
US3842492A (en) 1974-10-22
JPS5135349B1 (enExample) 1976-10-01
DE2159530A1 (de) 1972-07-13
DE2159530B2 (de) 1980-05-29
FR2118154A1 (enExample) 1972-07-28
CA933673A (en) 1973-09-11
DE2159530C3 (de) 1981-02-05
FR2118154B1 (enExample) 1976-06-04
IT943262B (it) 1973-04-02
NL7018378A (enExample) 1972-06-20

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee