FR2707059B1 - Circuit generateur d'impulsions d'horloge pour des circuits logiques a commande par impulsions d'horloge - Google Patents

Circuit generateur d'impulsions d'horloge pour des circuits logiques a commande par impulsions d'horloge

Info

Publication number
FR2707059B1
FR2707059B1 FR9407447A FR9407447A FR2707059B1 FR 2707059 B1 FR2707059 B1 FR 2707059B1 FR 9407447 A FR9407447 A FR 9407447A FR 9407447 A FR9407447 A FR 9407447A FR 2707059 B1 FR2707059 B1 FR 2707059B1
Authority
FR
France
Prior art keywords
clock pulse
generator circuit
logic circuits
pulse generator
controlled logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9407447A
Other languages
English (en)
French (fr)
Other versions
FR2707059A1 (en:Method
Inventor
Michael Albert
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
Original Assignee
Deutsche ITT Industries GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH filed Critical Deutsche ITT Industries GmbH
Publication of FR2707059A1 publication Critical patent/FR2707059A1/fr
Application granted granted Critical
Publication of FR2707059B1 publication Critical patent/FR2707059B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Manipulation Of Pulses (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
FR9407447A 1993-06-26 1994-06-17 Circuit generateur d'impulsions d'horloge pour des circuits logiques a commande par impulsions d'horloge Expired - Fee Related FR2707059B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE4321315A DE4321315C1 (de) 1993-06-26 1993-06-26 Takterzeugungsschaltung für taktgesteuerte Logikschaltungen

Publications (2)

Publication Number Publication Date
FR2707059A1 FR2707059A1 (en:Method) 1994-12-30
FR2707059B1 true FR2707059B1 (fr) 1997-02-28

Family

ID=6491317

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9407447A Expired - Fee Related FR2707059B1 (fr) 1993-06-26 1994-06-17 Circuit generateur d'impulsions d'horloge pour des circuits logiques a commande par impulsions d'horloge

Country Status (5)

Country Link
US (1) US5440250A (en:Method)
JP (1) JP3568987B2 (en:Method)
DE (1) DE4321315C1 (en:Method)
FR (1) FR2707059B1 (en:Method)
NL (1) NL194854C (en:Method)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3441780B2 (ja) * 1994-02-21 2003-09-02 日本テキサス・インスツルメンツ株式会社 クロック信号生成回路
US5670899A (en) * 1994-11-21 1997-09-23 Yamaha Corporation Logic circuit controlled by a plurality of clock signals
JPH08148982A (ja) * 1994-11-21 1996-06-07 Yamaha Corp 半導体集積回路
US5550503A (en) * 1995-04-28 1996-08-27 Motorola, Inc. Circuits and method for reducing voltage error when charging and discharging a capacitor through a transmission gate
US6069498A (en) * 1995-05-11 2000-05-30 Siemens Aktiengesellschaft Clock generator for CMOS circuits with dynamic registers
US5568100A (en) * 1995-09-22 1996-10-22 Lucent Technologies Inc. Synchronous power down clock oscillator device
US5867453A (en) * 1998-02-06 1999-02-02 Taiwan Semiconductor Manufacturing Co., Ltd. Self-setup non-overlap clock generator
US6169704B1 (en) 1998-05-20 2001-01-02 Micron Technology, Inc. Apparatus and method for generating a clock within a semiconductor device and devices and systems including same
US6445644B2 (en) 1998-05-20 2002-09-03 Micron Technology, Inc. Apparatus and method for generating a clock within a semiconductor device and devices and systems including same
DE19825216A1 (de) * 1998-06-05 1999-12-09 Siemens Ag Inverterschaltung
US6912139B2 (en) * 2002-11-14 2005-06-28 Fyre Storm, Inc. Multi-channel control methods for switched power converters
JPWO2004082142A1 (ja) * 2003-03-13 2006-06-15 富士通株式会社 論理回路
US7205805B1 (en) 2004-11-02 2007-04-17 Western Digital Technologies, Inc. Adjusting power consumption of digital circuitry relative to critical path circuit having the largest propagation delay error
US7129763B1 (en) 2004-11-08 2006-10-31 Western Digital Technologies, Inc. Adjusting power consumption of digital circuitry by generating frequency error representing error in propagation delay
US7378876B2 (en) * 2006-03-14 2008-05-27 Integrated Device Technology, Inc. Complementary output inverter
US7486060B1 (en) 2006-03-30 2009-02-03 Western Digital Technologies, Inc. Switching voltage regulator comprising a cycle comparator for dynamic voltage scaling
US8067970B2 (en) * 2006-03-31 2011-11-29 Masleid Robert P Multi-write memory circuit with a data input and a clock input
US7551383B1 (en) 2006-06-28 2009-06-23 Western Digital Technologies, Inc. Adjusting voltage delivered to disk drive circuitry based on a selected zone
US7330019B1 (en) 2006-10-31 2008-02-12 Western Digital Technologies, Inc. Adjusting on-time for a discontinuous switching voltage regulator
US7733189B1 (en) 2007-09-14 2010-06-08 Western Digital Technologies, Inc. Oscillator comprising foldover detection
US8085020B1 (en) 2008-06-13 2011-12-27 Western Digital Technologies, Inc. Switching voltage regulator employing dynamic voltage scaling with hysteretic comparator
US8937404B1 (en) 2010-08-23 2015-01-20 Western Digital Technologies, Inc. Data storage device comprising dual mode independent/parallel voltage regulators

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5020421B1 (en:Method) * 1968-06-03 1975-07-15
US4379974A (en) * 1980-09-10 1983-04-12 Mostek Corporation Delay stage for a clock generator
JPS5787620A (en) * 1980-11-20 1982-06-01 Fujitsu Ltd Clock generating circuit
JPS5881334A (ja) * 1981-11-11 1983-05-16 Hitachi Ltd 情報処理装置
WO1983004149A1 (en) * 1982-05-10 1983-11-24 Western Electric Company, Inc. Cmos integrated circuit
JPS59121697A (ja) * 1982-12-27 1984-07-13 Toshiba Corp シフトレジスタ
JPS60154709A (ja) * 1984-01-25 1985-08-14 Toshiba Corp クロツク信号発生回路
JPS61296821A (ja) * 1985-06-26 1986-12-27 Hitachi Micro Comput Eng Ltd 半導体集積回路装置
US4654599A (en) * 1985-07-05 1987-03-31 Sperry Corporation Four phase clock signal generator
JPH0691431B2 (ja) * 1987-03-02 1994-11-14 沖電気工業株式会社 フリツプフロツプ回路用クロツク制御回路
US4815041A (en) * 1987-03-19 1989-03-21 American Telephone And Telegraph Company Current surge elimination for CMOS devices
JPS641200A (en) * 1987-06-23 1989-01-05 Toshiba Corp Semiconductor integrated circuit
JPH07120225B2 (ja) * 1988-04-15 1995-12-20 富士通株式会社 半導体回路装置
DE58908782D1 (de) * 1989-09-22 1995-01-26 Itt Ind Gmbh Deutsche Zweiphasentaktgenerator.
IT1244205B (it) * 1990-12-19 1994-07-08 Sgs Thomson Microelectronics Circuito di generazione di un clock di scansione in un dispositivo di analisi operativa di tipo seriale per circuito integrato
US5140174A (en) * 1991-01-25 1992-08-18 Hewlett-Packard Co. Symmetric edge true/complement buffer/inverter and method therefor
US5280203A (en) * 1992-05-15 1994-01-18 Altera Corporation Look-ahead asynchronous register set/reset in programmable logic device
US5315181A (en) * 1993-07-07 1994-05-24 Maxtor Corporation Circuit for synchronous, glitch-free clock switching

Also Published As

Publication number Publication date
NL194854B (nl) 2002-12-02
JPH07154211A (ja) 1995-06-16
US5440250A (en) 1995-08-08
NL9401042A (nl) 1995-01-16
DE4321315C1 (de) 1995-01-05
NL194854C (nl) 2003-04-03
JP3568987B2 (ja) 2004-09-22
FR2707059A1 (en:Method) 1994-12-30

Similar Documents

Publication Publication Date Title
DE59605218D1 (de) Monolithisch integrierter Oszillator
KR900005694A (ko) 트리거 신호에 따른 소정 펄스폭의 펄스 발생회로
KR970050067A (ko) 샘플 홀드 회로
JPS57160654A (en) Recording method in ink jet recording device
ATE282852T1 (de) Verfahren und schaltung um an zwei enden getakten daten zu empfangen
HU9402471D0 (en) Circuit for a transducer
FR2412880A1 (fr) Horloge notamment a sonnerie
KR970705760A (ko) 클럭 신호의 논리적인 결합에 의한 전자회로 테스팅 방법, 및 이러한 테스팅용 장치를 구비한 전자회로(A method for testing an electronic circuit by logically combining clock signals, and an electronic circuit provided with facilities for such testing)
GB1256752A (en:Method)
SU627493A1 (ru) Итеративна модель распределени потока вещества
CA2302020C (en) Interface circuit for full-custom and semi-custom clock domains
ES2053733T3 (es) Colorantes dispersos.
SU1683006A1 (ru) Устройство дл делени на два последовательных кода "золотой" пропорции
SU1661761A1 (ru) Генератор случайных чисел
SU1170440A1 (ru) Пороговое устройство
SU843204A1 (ru) Устройство дл формировани задержкии длиТЕльНОСТи иМпульСА
Ezekiel Three poems from a Hyderabad sequence
SU978336A1 (ru) Селектор импульсов по длительности
RU1774484C (ru) Переключатель
SU1181117A1 (ru) Фильтр дискретной информации
RU98113690A (ru) Устройство для моделирования системы радиосвязи
KR870006723A (ko) 펄스 정밀 지연회로
SU1529437A1 (ru) Селектор импульсов по длительности
SU1312743A1 (ru) Устройство дл декодировани кода Миллера
SE9803051D0 (sv) Method and arrangement for duty cycle enlargement

Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20090228