ATE282852T1 - Verfahren und schaltung um an zwei enden getakten daten zu empfangen - Google Patents

Verfahren und schaltung um an zwei enden getakten daten zu empfangen

Info

Publication number
ATE282852T1
ATE282852T1 AT00910194T AT00910194T ATE282852T1 AT E282852 T1 ATE282852 T1 AT E282852T1 AT 00910194 T AT00910194 T AT 00910194T AT 00910194 T AT00910194 T AT 00910194T AT E282852 T1 ATE282852 T1 AT E282852T1
Authority
AT
Austria
Prior art keywords
circuit
data
receiving data
rate
edges
Prior art date
Application number
AT00910194T
Other languages
English (en)
Inventor
Kha Nguyen
Original Assignee
Qlogic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qlogic Corp filed Critical Qlogic Corp
Application granted granted Critical
Publication of ATE282852T1 publication Critical patent/ATE282852T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Circuits Of Receivers In General (AREA)
  • Bus Control (AREA)
  • Communication Control (AREA)
AT00910194T 1999-02-16 2000-02-16 Verfahren und schaltung um an zwei enden getakten daten zu empfangen ATE282852T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/249,873 US6317842B1 (en) 1999-02-16 1999-02-16 Method and circuit for receiving dual edge clocked data
PCT/US2000/003862 WO2000049485A1 (en) 1999-02-16 2000-02-16 Method and circuit for receiving dual edge clocked data

Publications (1)

Publication Number Publication Date
ATE282852T1 true ATE282852T1 (de) 2004-12-15

Family

ID=22945371

Family Applications (1)

Application Number Title Priority Date Filing Date
AT00910194T ATE282852T1 (de) 1999-02-16 2000-02-16 Verfahren und schaltung um an zwei enden getakten daten zu empfangen

Country Status (8)

Country Link
US (1) US6317842B1 (de)
EP (1) EP1163569B1 (de)
JP (1) JP2003523548A (de)
AT (1) ATE282852T1 (de)
AU (1) AU3232700A (de)
CA (1) CA2362174A1 (de)
DE (1) DE60015939T2 (de)
WO (1) WO2000049485A1 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6470397B1 (en) * 1998-11-16 2002-10-22 Qlogic Corporation Systems and methods for network and I/O device drivers
JP3278621B2 (ja) * 1998-12-24 2002-04-30 松下電器産業株式会社 データ伝送装置
US6606360B1 (en) * 1999-12-30 2003-08-12 Intel Corporation Method and apparatus for receiving data
US6892252B2 (en) * 2000-09-21 2005-05-10 Michael Tate Asymmetric data path media access controller
DE102004010562B4 (de) 2004-03-01 2008-04-24 Infineon Technologies Ag Schnittstellenvorrichtung und Verfahren zur Synchronisation von Daten
DE102004011672B4 (de) * 2004-03-10 2007-04-05 Texas Instruments Deutschland Gmbh Vorrichtung zur Datensynchronisation
US7242235B1 (en) * 2005-02-25 2007-07-10 Exar Corporation Dual data rate flip-flop
US20080183948A1 (en) * 2007-01-31 2008-07-31 Satoshi Sugawa Flash memory system with higher data transmission rate and method thereof
WO2010002943A1 (en) * 2008-07-01 2010-01-07 Lsi Corporation Methods and apparatus for interfacing between a flash memory controller and a flash memory array
TWI389104B (zh) * 2009-02-11 2013-03-11 Via Tech Inc 支援硬碟最高傳輸速率的硬碟存取方法及系統
US10996272B2 (en) * 2014-08-27 2021-05-04 Teradyne, Inc. One-shot circuit

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US5758188A (en) 1995-11-21 1998-05-26 Quantum Corporation Synchronous DMA burst transfer protocol having the peripheral device toggle the strobe signal such that data is latched using both edges of the strobe signal
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Also Published As

Publication number Publication date
DE60015939T2 (de) 2005-11-10
US6317842B1 (en) 2001-11-13
JP2003523548A (ja) 2003-08-05
AU3232700A (en) 2000-09-04
WO2000049485A1 (en) 2000-08-24
EP1163569B1 (de) 2004-11-17
CA2362174A1 (en) 2000-08-24
EP1163569A1 (de) 2001-12-19
EP1163569A4 (de) 2002-05-15
DE60015939D1 (de) 2004-12-23

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