FR2456991A1 - Circuit generateur de tension de lecture de memoire permettant d'adapter des memoires mortes programmables effacables a des circuits utilisant une tension de polarisation du substrat - Google Patents
Circuit generateur de tension de lecture de memoire permettant d'adapter des memoires mortes programmables effacables a des circuits utilisant une tension de polarisation du substratInfo
- Publication number
- FR2456991A1 FR2456991A1 FR8010598A FR8010598A FR2456991A1 FR 2456991 A1 FR2456991 A1 FR 2456991A1 FR 8010598 A FR8010598 A FR 8010598A FR 8010598 A FR8010598 A FR 8010598A FR 2456991 A1 FR2456991 A1 FR 2456991A1
- Authority
- FR
- France
- Prior art keywords
- voltage
- memory
- deadly
- programmable
- circuits
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000010287 polarization Effects 0.000 title abstract 3
- 239000000758 substrate Substances 0.000 title abstract 3
- 230000002498 deadly effect Effects 0.000 title abstract 2
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
Landscapes
- Read Only Memory (AREA)
- Power Sources (AREA)
- Measurement Of Current Or Voltage (AREA)
- Logic Circuits (AREA)
Abstract
CIRCUIT ASSOCIE A UNE MEMOIRE MORTE PROGRAMMABLE EFFACABLE INTEGREE AVEC DES CIRCUITS UTILISANT UNE POLARISATION DE SUBSTRAT DE FACON A PRODUIRE LA TENSION DE LECTURE DE LA MEMOIRE APPROPRIEE INDEPENDAMMENT DE LA TENSION DE POLARISATION DU SUBSTRAT. CE CIRCUIT COMPREND UN GENERATEUR 40 DE TENSION DE REFERENCE QUI MESURE CONTINUELLEMENT LA TENSION DE SEUIL D'UN TRANSISTOR DE MEMOIRE A DEUX PORTES NON PROGRAMMEES 60, 62 ET PRODUIT UNE TENSION DE REFERENCE EXACTEMENT EGALE A CETTE TENSION DE SEUIL ET UN CIRCUIT 42 ELEVATEUR DE TENSION QUI ACCROIT LA TENSION DE REFERENCE D'UNE VALEUR FIXE POUR OBTENIR UNE TENSION DE PORTE OPTIMALE DES TRANSISTORS DE MEMOIRE 38 ET UN TEMPS D'ACCES DE LA MEMOIRE OPTIMAL. APPLICATION NOTAMMENT AUX MEMOIRES DE MICROPROCESSEURS INTEGREES SUR UNE UNIQUE MICROPLAQUETTE AVEC L'UNITE DE TRAITEMENT DU PROCESSEUR.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US3861279A | 1979-05-14 | 1979-05-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2456991A1 true FR2456991A1 (fr) | 1980-12-12 |
FR2456991B1 FR2456991B1 (fr) | 1985-11-22 |
Family
ID=21900899
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8010598A Expired FR2456991B1 (fr) | 1979-05-14 | 1980-05-12 | Circuit generateur de tension de lecture de memoire permettant d'adapter des memoires mortes programmables effacables a des circuits utilisant une tension de polarisation du substrat |
Country Status (5)
Country | Link |
---|---|
JP (1) | JPS59917B2 (fr) |
DE (1) | DE3017960C2 (fr) |
FR (1) | FR2456991B1 (fr) |
GB (1) | GB2049327B (fr) |
IT (1) | IT1129217B (fr) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5693363A (en) * | 1979-12-04 | 1981-07-28 | Fujitsu Ltd | Semiconductor memory |
IE55327B1 (en) * | 1981-12-29 | 1990-08-15 | Fujitsu Ltd | Nonvolatile semiconductor memory circuit |
EP0189594B1 (fr) * | 1984-12-28 | 1992-08-12 | Nec Corporation | Dispositif de mémoire semi-conductrice non-volatile |
JPS63149534A (ja) * | 1986-12-13 | 1988-06-22 | Hokutou Koki Kogyo Kk | 重心検出器 |
US5448517A (en) * | 1987-06-29 | 1995-09-05 | Kabushiki Kaisha Toshiba | Electrically programmable nonvolatile semiconductor memory device with NAND cell structure |
US5877981A (en) * | 1987-06-29 | 1999-03-02 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device having a matrix of memory cells |
US6034899A (en) * | 1987-06-29 | 2000-03-07 | Kabushiki Kaisha Toshiba | Memory cell of nonvolatile semiconductor memory device |
US6545913B2 (en) | 1987-06-29 | 2003-04-08 | Kabushiki Kaisha Toshiba | Memory cell of nonvolatile semiconductor memory device |
JP3109736B2 (ja) * | 1987-07-31 | 2000-11-20 | 株式会社東芝 | 半導体集積回路と浮遊ゲート型メモリセルの読み出し駆動方法 |
-
1980
- 1980-02-26 GB GB8006449A patent/GB2049327B/en not_active Expired
- 1980-04-17 IT IT67601/80A patent/IT1129217B/it active
- 1980-05-10 DE DE3017960A patent/DE3017960C2/de not_active Expired
- 1980-05-12 FR FR8010598A patent/FR2456991B1/fr not_active Expired
- 1980-05-13 JP JP55062349A patent/JPS59917B2/ja not_active Expired
Non-Patent Citations (1)
Title |
---|
Néant * |
Also Published As
Publication number | Publication date |
---|---|
IT1129217B (it) | 1986-06-04 |
JPS59917B2 (ja) | 1984-01-09 |
GB2049327A (en) | 1980-12-17 |
DE3017960A1 (de) | 1980-11-20 |
FR2456991B1 (fr) | 1985-11-22 |
IT8067601A0 (it) | 1980-04-17 |
JPS55153195A (en) | 1980-11-28 |
DE3017960C2 (de) | 1984-08-30 |
GB2049327B (en) | 1983-03-30 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
ST | Notification of lapse |