GB2049327A - Memory read voltage circuitry for adapting EPROMs to circuits employing substrate bias voltage - Google Patents

Memory read voltage circuitry for adapting EPROMs to circuits employing substrate bias voltage Download PDF

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GB2049327A
GB2049327A GB8006449A GB8006449A GB2049327A GB 2049327 A GB2049327 A GB 2049327A GB 8006449 A GB8006449 A GB 8006449A GB 8006449 A GB8006449 A GB 8006449A GB 2049327 A GB2049327 A GB 2049327A
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voltage
transistor
gate
eprom
threshold
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GB2049327B (en )
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Fairchild Semiconductor Corp
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Fairchild Semiconductor Corp
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/26Sensing or reading circuits; Data output circuits

Abstract

Circuitry included on an MOS integrated circuit chip with a CPU and an EPROM for developing the proper EPROM read voltage independently of the CPU substrate bias voltage. The circuit includes a voltage reference generator that continually measures a dual gate EPROM transistor and outputs a reference voltage precisely equal to its threshold voltage, and a controlled high voltage generator that increases said reference voltage by a fixed value for achieving an optimum EPROM access time and gate voltage. <IMAGE>

Description

SPECIFICATION Memory read voltage circuitry for adapting eproms to circuits employing substrate bias voltage Description This invention relates to erasable, programmable, read-only memories and particularly to circuitry for permitting an EPROM to be used on the same circuit chip with circuits employing substrate bias voltages such as conventional MOS integrated circuit microprocessors, or the like.

Virtually all large scale integrated n-channel MOS circuits operate with a substrate bias voltage. The latest approach is to integrate the bias generator on the circuit chip and to make the bias voltage variable and dependent upon factors such as the threshold voltages of the various transistors, the applied power supply voltage (Vcc), temperature and aging.

Awell designed substrate bias generator may produce an output voltage in the range of - 1.0 to -7.0 volts with an applied Vc ; power supply voltage of 5.0 volts.

Unfortunately, erasable programmable read-only memory (EPROM) transistors must have a threshold voltage in the order of +2.0 to 5.0 volts to achieve good programability. When an EPROM transistor having normal threshold voltage of between 1.5 to 2.5 volts is subjected to a substrate bias voltage, its threshold voltage may be increased up to approximately 7 volts, depending upon the resistivity of the substrate material and substrate voltage. Thus, with the power supply voltage (Vcc) of 5.0 volts, it is impossible to turn on any transistor with a threshold voltage above 5.0 volts. Furthermore, if the total threshold voltage above 5.0 volts. Furthermore, if the total threshold voltage of an EPROM transistor subjected to substrate bias were lower than the 5.0 volts Vcc level, for example at 4.0 volts, it may be turned on but may take an extremely long time, for example, hours or days.

Because of the above-described difficulties, designers of modern circuits, such as single chip microprocessors, have heretofore found it necessary to make an election between incorporating erasable programmable read-only memories on the circuit chip, thus losing all advantages of the substrate bias techniques, or employing substrate bias and incorporating some memory other than an EPROM.

The present invention solves the above outlined problem by circuitry that generates the proper EPROM read voltage independently of variations in substrate bias voltage. The circuitry of the invention includes a reference generator that constantly measures the threshold voltage of an unprogrammed EPROM control transistor on the same chip and which is affected by the same substrate bias voltage, temperature, aging and any other factors that may have an effect on the memory transistors. The output of this reference generator is a voltage precisely equal to the threshold voltage of EPROM transistors and is applied to a high voltage generating cicuit which adds a predetermined fixed level of voltage to the reference voltage to achieve the desired access time of the memory.

Description of the drawings In the drawings which illustrate a preferred embodiment of the invention: Figure 1 is a circuit diagram of a small portion of a typical EPROM illustrating the connection of the reference generator and high voltage generator of the invention; Figure 2 is a schematic diagram of the reference generator and high voltage generator illustrated as blocks in Figure 1; Figures 3A through 3D illustrate various symbols used in the schematic diagram of Figure 2 and their respective equivalent circuits; and Figure 4 illustrates voltage-time diagrams of signals at various corresponding points in the circuitry of Figure 2.

Detailed description Figure 1 shows a circuit diagram of a small portion of an EPROM matrix 10 together with associated X-select circuitry 12 and Y-select circuitry 14. The X-select circuitry 12 may be a typical decoder circuit which, when energized, selects one of the horizontal EPROM gate conductor lines, such as lines 16, 18 and 20, to provide an EPROM read voltage to all memory cells associated with that particular X-line.

Similarly, the Y-select circuitry 14 receives an input signal from a suitable Y-line decoder and precharges one of a plurality of vertical lines, such as lines 22, 24, 26 or 28. The memory cell located at the intersection of the selected X-line and selected Y-line is then interrogated by the read signal and a state of conduction or non-conduction, representing an on/ off binary state, may be detected by an output buffer amplifier, such as amplifier 30.

EPROM cells deposited on integrated circuit chips are usually formed of a dual gate transistor, such as the transistor 38 at the intersection of Y-line 22 and X-line 16. The dual gate transistor is a silicon gate MOS transistor having a floating gate element formed between the n-channel and the control gate element and insulated therefrom. This central or floating gate has little effect on the conduction of the transistor unless it is made to contain an electron charge. Thus, to program an EPROM transistor, a voltage higher than the normal operating voltage is applied to the gate and drain elements so that the floating gate element will absorb and hold a small electron charge. This floating gate charge increases the conduction threshold of the control gate transistor from a low of approximately 2 volts to a level of 10 volts or higher, depending upon the quantity of charge accepted.Therefore, an EPROM matrix comprising a plurality of charged and uncharged dual gate transistors may be read by applying a read voltage at least equal to the threshold voltage of an unprogrammed, or uncharged, transistor but well below the threshold level of a charged or programmed transistor.

As previously discussed, it has heretofore been impossible to incorporate EPROMs, such as the dual gate transistor cell matrix described herein, on circuit chips with a negative substrate bias voltage.

This is because the bias voltage would materially increase the EPROM transistor threshold voltage by varying amounts depending upon the varying substrate bias voltage level. The circuitry of Figure 1 includes a reference generator 40 which, as previously mentioned, measures the threshold voltage of an unprogrammed test EPROM transistor on the same substrate and subject to the same bias voltage.

Reference generator 40 therefore generates a D.C.

output reference voltage equal to the threshold voltage of the unprogrammed EPROM transistor and therefore all other unprogrammed EPROM transistors on the same chip and affected by the same substrate bias voltage. High voltage generator 42 receives that reference voltage and, in order to increase the access speed of the memory to a level of approximately 200 nanoseconds, increases the voltage by a fixed level of, for example, 2.5 volts. The conductor 44 at the output of high voltage generator 42 is connected to the drain electrodes of a plurality of gate transistors, such as transistors 46, 48 and 50, the gates of which are connected to the horizontal X-lines of the matrix 10 through light depletion transistors that will be described later.The source elements of these transistors are connected directly to the control gate of the EPROM transistors in their associated line and the control gates of the transistors 46, 48 and 50 are connected to the appropriate X-lines at the output of the X-select circuit 12.

Figure 2 is a schematic diagram illustrating the details of the reference generator 40 and high voltage generator 42 of Figure 1. It will be noted that the schematic diagram of Figure 2 contains transistors and various inverter circuits illustrated with various identifying symbols. These various circuits are illustrated for convenience in Figure 3.

Figures 3A through 3D illustrate the various inverter circuits shown in Figure 2. Illustrated in Figure 3A is the symbol for an inverter containing a small triangle. The equivalent schematic diagram is illustrated directly below the inverter symbol and in cludes a light depletion load transistor 52 coupled between Vcc and the output terminal. The gate element of transistor 52 is also coupled to the output terminal and to the drain of a transistor 53, the source of which is coupled to ground reference and the gate element of which represents the circuit input.

Figure 3B is identical with the circuitry of Figure 3A except that the solid triangle within the inverter symbol represents a heavy depletion load so that the depletion transistor 54 is always on and represents no voltage drop between Vcc and the outputter minal.

Figure 3A illustrates an inverter symbol containing the letter "E". This designates an enhancement transistor 56 coupled between Vcc and the output with the gate of transistor 56 coupled to the Vcc source. Transistor 56 is therefore always on but introduces one threshold voltage drop between Vcc and the output.

Figure 3D illustrates the symbol for a gate, the high or low output of which is governed by the inputs A or B, as illustrated in the accompanying schematic diagram. It should be noted that the transistor 58 of Figure 3D may be an enhancement lettered with the "E", a light depletion load transistor with the hollow triangle contained therein, or a heavy depletion transistor with the solid triangle.

Returning now to the description of the schematic diagram of Figure 2, the reference generator included within the dashed box 40 contains one or more unprogrammed, or uncharged, EPROM transistors 60, 62 coupled between node 64 and ground reference Since the reference voltage control transistor 88, to be subsequently described, requires a gate voltage substantially higher than the Vcc supplied to the circuit, a voltage pumping circuit is provided. A Vcc potential of typically 5 volts is applied to the terminal 66 where it is raised to a higher voltage of approximately 7.5 volts by the voltage pump comprising transistors 68, 70 and 72 in series. The gate and drain off transistor 68 are coupled together and the source element is coupled to the gate and drain of transistor 70.The gate of transistor 70 is also capacitor coupled to one phase of the associated two-phase computer clock circuitry. The source of transistor 70 is coupled to the gate and drain of transistor 72, the gate element of which is capacitor coupled to the second phase of the two-phase clock circuitry. The pumping action by the two clock phases produces a high frequency halfwave A.C. signal above the Vcc base potential and this half-wave signal is filtered by the capacitor 74 connected between ground reference and the source element of transistor 72. The voltage then appearing at the source of transistor 72 is considerably higher than the Vcc voltage and is typically approximately 7.5 volts.

In order to provide power to the circuitry more rapidly at start-up, the reference generator preferably includes a start-up circuit which comprises the transistor 76 coupled between Vcc terminal and the conductor 78. The gate of transistor 76 is coupled to the output of an inverter 80 which derives its input from the node 64 so that when the potential on node 64 is at its zero level, the inverter 80 will apply a positive signal to the gate of transistor 76 so that the Vcc potential is initially applied to conductor 78.

Thereafter, when node 64 acquires a potential, the inverter 80 will turn off transistor 76.

The source element of transistor 72 in the voltage pump circuit applies the higher voltage through conductor 82 to a heavy depletion load transistor 84 coupled between conductors 82 and 78. The gate element of transistor 84 is coupled to conductor 78 so that the transistor 84 presents a varying resistance depending upon the voltage level on conductor 78. Conductor 78 is coupled to the node 64 through an enhancement transistor 86, the gate element of which is coupled to conductor 78. Transistor 86 is therefore always on and introduces a small voltage drop equal to its threshold voltage. The voltage between node 64 and ground reference is determined by the threshold voltage of the EPROM transistors 60 or 62. Thus, a voltage divider action is developed between the high voltage conductor 82 and ground reference and comprises a series resistance of transistor 84, the threshold of the enhancement transistor 86 and the threshold of the EPROM transistor 60 or 62, and the node 64 will always be at a level equal to the threshold of an unprogrammed EPROM transistor.

Conductor 78 will be at a level equal to the threshold of the EPROM transistor plus the threshold of the enhancement transistor 86. Conductor 78 is connected to the gate electrode of an enhancement transistor 88, the source element of which is connected to the Vcc terminal 66. The voltage appearing at the drain element of the transistor 88 will be equal to the voltage applied to its gate less the threshold voltage of transistor 88. Since conductor 78 was at a potential of the threshold of EPROM transistors 60 or 62 plus the threshold voltage of transistor 86, the voltage at the output of transistor 88 will be one threshold voltage lower than the voltage appearing on conductor 78 or will be precisely the same as the threshold voltage of the unprogrammed EPROM transistors 60 or 62.

Illustrated in the schematic diagram of the reference generator 40 is a pair of series connected transistors 90 and 92 connected in parallel with EPROM transistors 60 and 62 and between the node 64 and ground potential. These transistors are dual gate transistors similarto the EPROM transistors 60 and 62; however, they are formed so that the two gates within each transistor are connected together so that their individual threshold voltages are approximately half that of the EPROM transistors 60,62 with the floating gate. The purpose of the series connected transistors 90 and 92 is to provide substantially the identical threshold voltage on node 64 in the event that both the EPROM transistors 60 or 62 should become somehow programmed and fail to establish the proper EPROM threshold voltage on node 64.Transistors 90 and 92 are therefore not necessary to the operation of the circuit but are preferably included as a standby safety group.

The output of the reference generator 40 carries a voltage precisely equal to the threshold voltage of an unprogrammed EPROM transistor as described above. If this voltage level were applied to the EPROM transistors in the matrix 10 of Figure 1, the unprogrammed memorytransistorwould produce an output but the access time of the memory may be a a matter of hours. To improve the access time to a usable value, it is necessary to increase the read or EPROM transistor gate voltage above the threshold level of the unprogrammed EPROM transistors. If the read voltage were unnecessarily high, the programmed EPROM transistors may erroneously produce an output and, even if the read voltage were sufficiently lowered to prevent such a faulty output, the reading of the matrix with a higher than necessary voltage may in time destroy the program.It is therefore necessary that a precise predetermined voltage level above the unprogrammed threshold voltage be generated. As previously explained, this excess read voltage controls the access speed of the memory, and it has been found that to obtain an approximate 200 nanosecond access time, a read voltage of 2-1/2 volts plus the EPROM threshold voltage must be used. If slower access times are desired, slightly lower excess voltages may be employed.

The EPROM transistor threshold-reference voltage generated within the reference generator 40 is applied to the high voltage generator 42 where it is switched by a gating transistor 96, the drain electrode of which is coupled to the output conductor 44 which is connected to the source electrode of all X-select gating transistors such as the transistor 46 referred to in connection with Figure 1. The drain electrode of transistor 96 is also coupled through a gate transistor 98 to ground reference and the control gate of transistor 98 is coupled to input terminal 100 to which is applied an active low read-phase signal from associated computer circuit ry.Thus, until-the ground-going read signal is applied to the input terminal 100, the transistor 98 is "on" to ground conductor 44, and upon the application of the read-phase signal, transistor 98 is turned "off" to remove conductor44 from ground.

In order to assist in an understanding of the circuitry of the high voltage generator 42 of Figure 2, typical time-voltage curves are illustrated in Figure 4 and refer to signals appearing at various points in the circuitry identified by corresponding letter desig nations. Thus, curve A of Figure 4 represents the ground-going read-phase signal applied to terminal 100 of Figure 2. The signal is applied to the gate of transistor 98 to render it non-conductive and is also applied to one input terminal of a NOR gate 102 which, prior to the application of the ground-going signal, produced a low output which was applied through transistor 104 to the gate of transistor 96.

The gate of transistor 104 is coupled directly to the Vde source so that a high voltage is applied to fully turn on transistor 96.

The read-phase signal applied to terminal 100 is also directed through a delay circuit including a heavy depletion inverter 106 in series with a RC circuit comprising transistor 108 which has its gate coupled back to its input source and therefore represents a resistance, and the grounded capacitor 110. The output of this RC delay line is represented by curve B of Figure 4 which is normally at a low state and rises to its high level approximately 250 nanoseconds after the ground-going signal is ap plied to terminal 100. The delay line also includes an enhancement inverter 112, the output voltage level of which is controlled by the signal output of transistor 108 as represented by curve B of Figure 4.

Therefore, the output of the inverter 112 is represented by the same signal B of Figure 4 and this signal is applied to the second input terminal of the NOR gate 102 to produce at its output a signal represented by curve C of Figure 4. Thus transistor 96 in the high voltage generator circuit 42 is only turned on for a period of approximately 250 nanoseconds as represented by the curve C.

The output of the inverter 112 is applied to the input of a light load depletion inverter 114 which receives its second input from the terminal 100.

When the input B to inverter 114 is high, its output is grounded and when the input goes to its low state, the inverter is enabled to accept the signal A at the terminal 100. The result is a signal represented by curve D of Figure 4 which is applied to the input of inverter 116. Inverter 116 is shunted by a circuit -comprising inverter 118 and transistor 120, the gate element of which is coupled to the Vcc source so that its output drain will apply a full Vcc signal to control inverter 116, which produces an output signal as represented by the curve E of Figure 4.

The output signal from inverter 116 is applied to one side of a capacitor 122, the other terminal of- which is connected to conductor 44 and to the drain electrode of the gating transistor 96. As previously mentioned, transistor-96 is turned on, and transistor 98 is turned off, by the application of the read phase signal to terminal 100. Approximately 250 nanose conds thereafter, transistor 96 is turned off while transistor 98 remains off. As illustrated-by curve F of Figure 4, the output signal of inverter 116 is applied to the capacitor 122 at the instant that transistor 96 is turned off. This has the effect of increasing the voltage on conductor 44 by a value dependent upon the ratio of the capacitance of capacitor 122 to the total circuit capacitance 124 in a selected X-line of the EPROM matrix 10.In the preferred embodiment, it is desired to increase the EPROM transistor threshold voltage at the drain terminal of transistor 96 by a voltage equal to one-half Vcc. Therefore, capacitor 122 is carefully selected so that its capaci tance is equal to the total X-line circuit capacitance 124. The signal appearing at point F in the circuitry is therefore represented by the curve F of Figure 4, the first step of which represents the EPROM transistor threshold voltage, the second or rounded step of which represents one-half Vcc. Obviously the voltage drops back to its low level upon cessation of the read signal at terminal 100 and the resulting conduction through transistor 98 to ground.

The EPROM gate or read voltage applied to the conductor 44 is now conducted through a gating transistor 46 to the control gate of the selected EPROM transistor. If the X-select circuit 12 has selected the XO line 16, the 5-volt Vcc signal from the circuit 12 (curve G of Figure 4) is applied through the light depletion transistor 126 to the gate of transistor 46. The gate of transistor 126 is coupled to Vcc and the gate of transistor 46 will receive the full Vcc voltage. When the high voltage generator 42 subse quently outputs on to conductor 44, a portion of this higher voltage is capacitively coupled to the gate of transistor 46 as shown by the dashed capacitor 128 representing inter-circuit capacity. This increases the gate voltage of transistor 46 by an additional amount over its normal Vcc level, as illustrated by curve H of Figure 4. This additional amount is proportional to the ratio of the capacitance of 128 to the sum of capacitances 128 and 130 between the gate of transistor 46 and ground. The transistor 46, novwwith the high gate voltage, is fully "on" and will provide the necessary high read voltage to the gates of the EPROM transistors associated with the X-line 16, as illustrated by the curve J of Figure 4.

Claims (14)

  1. 1. Read voltage circuitry for providing a read voltage to dual gate EPROM transistors in a memory included with circuitry employing substrate bias voltage, said read voltage circuitry including: reference voltage generating circuitry for measur- ing the threshold voltage of a sample unprogram- - med EPROM transistor in said generating circuitry and subjected to the substrate bias voltage, and for generating an output reference voltage equal to said thres#hold voltage; a high voltage generator coupled to said reference voltage generating circuitry and responsive to said output reference voltage for generating an output signal equal to said threshold voltage plus a predetermined constant excess voltage; and a gating transistor coupled between the output of said high voltage generator and each one of a plurality of EPROM transistor gate conductors, the gate electrode of said gating transistor being coupled to the output of an X-select circuit associated with said memory.
  2. 2. The circuit claimed in Claim 1 wherein the total output voltage generated by said high voltage generator is higherthan the threshold voltage of an unprogrammed EPROM transistor and lower than the threshold voltage of the programmed EPROM transistor.
  3. 3. The circuitry claimed in Claim 2 wherein said high voltage generator is responsive to an externally applied read pulse of a first pulse duration and includes delay circuitry that limits the reference voltage received from said reference voltage gener ating circuitry to a pulse of a second duration shorter than said first pulse duration.
  4. 4. The-circuitry claimed in Claim 3 wherein said high voltage generator includes a capacitor coupled between the output conductor of said generator and the output of said delay circuitry, said capacitor being charged to a first level by said reference voltage pulse of a second duration, said delay circuitry providing to said capacitor an additional charge upon termination of said first duration pulse.
  5. 5. The circuitry claimed in Claim 4wherein said additional charge reaches a total amplitude that is proportional to the circuitry Vec times the ratio of the capacitance of said capacitor to the circuit capacitance of the output conductor of said high voltage generator.
  6. 6. The circuitry claimed in Claim 2 wherein said reference volage generating circuitry includes at least one unprogrammed dual-gate EPROM tran sistor.
  7. 7. The circuitry claimed in Claim 6 further includ ing at least two series connected unprogrammable dual-gate transistors in parallel with said EPROM transistor, said series unprogrammable transistors providing substantially the same threshold voltage measurement of said EPROM transistor
  8. 8. The circuitry claimed in Claim 6 wherein said reference voltage generating circuitry output refer ence voltage is controlled by a control transistor coupled between Vcc and the reference generator output conductor, the voltage control electrode of said control transistor being coupled to said EPROM transistor and responsive to the threshold voltage of said EPROM transistorfor controlling the output level of said reference generating circuitry to the voltage level of its voltage control electrode minus the threshold voltage of said control transistor.
  9. 9. The circuitry claimed in Claim 8 wherein said EPROM transistor is coupled in series with a first transistor having a threshold voltage identical with the threshold voltage of said control transistor for increasing the measured EPROM transistor threshold voltage by an amount equal to the threshold voltage drop through said control transistor whereby said control transistor will produce an output voltage precisely equal to the threshold voltage of said EPROM transistor.
  10. 10. The circuitry as claimed in Claim 9 wherein said reference voltage generating circuitry includes voltage pumping means for increasing the amplitude of the voltage about the circuit Vcc level, said increased level being applied through said series first transistor and the EPROM transistor and applied to the control electrode of said control transistor.
  11. 11. The circuitry claimed in Claim 10 wherein said reference voltage generating circuitry includes a start-up circuit responsive to a low output of said voltage pumping means for directly applying a Vcc voltage level to the control electrode of said control transistor.
  12. 12. The circuitry claimed in Claim 6 wherein the control gate of said gating transistor is coupled to said X-select circuit outputthrough a transistor having its gate at a Vcc voltage level.
  13. 13. The circuitry claimed in Claim 12 wherein the voltage level on the control gate of said gating transistor is increased above Vcc level by an amount proportional to the output level of said voltage generating circuitry and the source-to-gate capacitance of said gating transistor, and is inversely proportional to the sum of said source-to-gate capacitance and the gate-to-ground capacitance.
  14. 14. Read voltage circuitry substantially as herein described with reference to the accompanying drawings.
GB8006449A 1979-05-14 1980-02-26 Memory read voltage circuitry for adapting eproms to circuits employing substrate bias voltage Expired GB2049327B (en)

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US3861279 true 1979-05-14 1979-05-14

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DE (1) DE3017960C2 (en)
FR (1) FR2456991B1 (en)
GB (1) GB2049327B (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0085260A2 (en) * 1981-12-29 1983-08-10 Fujitsu Limited Nonvolatile semiconductor memory circuit
EP0031643B1 (en) * 1979-12-04 1984-06-13 Fujitsu Limited Semiconductor memory device
US4924438A (en) * 1984-12-28 1990-05-08 Nec Corporation Non-volatile semiconductor memory including a high voltage switching circuit

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63149534A (en) * 1986-12-13 1988-06-22 Hokutou Koki Kogyo Kk Center-of-gravity detector
US5877981A (en) * 1987-06-29 1999-03-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having a matrix of memory cells
US6545913B2 (en) 1987-06-29 2003-04-08 Kabushiki Kaisha Toshiba Memory cell of nonvolatile semiconductor memory device
US6034899A (en) * 1987-06-29 2000-03-07 Kabushiki Kaisha Toshiba Memory cell of nonvolatile semiconductor memory device
US5448517A (en) * 1987-06-29 1995-09-05 Kabushiki Kaisha Toshiba Electrically programmable nonvolatile semiconductor memory device with NAND cell structure
JP3109736B2 (en) * 1987-07-31 2000-11-20 株式会社東芝 Read driving method of a semiconductor integrated circuit and the floating gate memory cell

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0031643B1 (en) * 1979-12-04 1984-06-13 Fujitsu Limited Semiconductor memory device
EP0085260A2 (en) * 1981-12-29 1983-08-10 Fujitsu Limited Nonvolatile semiconductor memory circuit
EP0085260A3 (en) * 1981-12-29 1983-11-16 Fujitsu Limited Nonvolatile semiconductor memory circuit
US4677590A (en) * 1981-12-29 1987-06-30 Fujitsu Limited Nonvolatile semiconductor memory circuit including dummy sense amplifiers
US4924438A (en) * 1984-12-28 1990-05-08 Nec Corporation Non-volatile semiconductor memory including a high voltage switching circuit

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FR2456991B1 (en) 1985-11-22 grant
DE3017960A1 (en) 1980-11-20 application
FR2456991A1 (en) 1980-12-12 application
JP1227061C (en) grant
DE3017960C2 (en) 1984-08-30 grant
JPS55153195A (en) 1980-11-28 application
GB2049327B (en) 1983-03-30 grant
JPS59917B2 (en) 1984-01-09 grant

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Effective date: 19950226