DE3017960A1 - MEMORY CIRCUIT - Google Patents

Description

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The invention relates to erasable programmable read-only memories and, more particularly, relates to circuits that which allow an EPROM to operate on the same circuit board with circuits where Substrate biases are used, for example integrated MOS microprocessor circuits of conventional design or the like «

Virtually all LSI (large scale integrated) n-channel MOS circuits operate with substrate bias. More recently, efforts are made to integrate the bias voltage on the circuit chip and to make the bias voltage is variable and upon certain factors dependent, _o e.g., the threshold voltages of the various transistors, the applied voltage ₍₀ V). Power, temperature, and

C C

aging o A substrate bias generator of good design can produce an output voltage of the order of -1.0 to -7s) 0 volts, with a voltage V der

CC

Power supply of 5.0 volts is present.

A disadvantage here is that transistors of erasable programmable read-only memories (EPROMs) must have a threshold voltage in the order of +2.0 to +5.0 volts, thus a good programmability is achieved between ₀ When a EPROM transistor with normal threshold voltage 1.5 to 2.5 volts of a substrate bias is applied, its threshold voltage can rise up to about 7 volts, depending on the resistivity of the substrate material and the substrate voltage. When the voltage (V_.)

Ct *

the power supply 5 ₅ O volts, it is therefore impossible, _s to enable any transistors having a threshold voltage above 5 0 volts in the on state. Incidentally, when the total threshold voltage is one of a substrate bias

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exposed EPROM transistor lower than the 5.0 volts of the V "level, for example 4 volts, it can be in the On-state, but it can take an extremely long time for this, for example hours or Days.

Because of these difficulties, modern circuit designs such as single chip microprocessors have hitherto been known Make a choice whether to be erasable programmable On-board read-only memories should be used, taking full advantage of the substrate biasing technique lost, or to work with substrate bias and then memories of another type, i.e. no EPROMs, to use.

The present invention solves the difficulties described by a circuit that provides the desired EPROM read voltage regardless of changes in the substrate bias generated. The circuit provided according to the invention contains a reference generator which the threshold voltage of an unprogrammed EPROM control transistor on the same die is constant, and which of the same Substrate bias, temperature, aging and other other factors that affect the properties of the memory transistors can influence. The output of this reference generator is a voltage which is exactly equal to the threshold voltage of EPROM transistors and they will be connected to a High-voltage generator circuit applied, which adds a predetermined fixed voltage level to the reference voltage in order to to get the desired access time of the memory.

Preferred embodiments of the invention are set out below described on the basis of the drawings:

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Fig. 1 is a circuit diagram of a small portion of an EPROM circuit usual design, and it shows the connection with the reference generator and the high-voltage generator according to the invention;

FIG. 2 shows a simplified circuit diagram of the reference generator and the high-voltage generator, which are shown in FIG. 1 in Block diagram are included;

3A show different in the schematic representation of Figure 2 ^s ^ symbols used and its equivalent circuits.

Fig. 4 shows voltage-time diagrams of signals at various in Fig. 2 designated points.

1 shows a simplified circuit diagram of a small portion of an EPROM matrix 10 together with an associated X selection circuit (select circuitry) 12 and a Y-selection circuit (select circuitry) 14. The X selection circuit 12 may be a Decoder circuit of the usual type which, when appropriately controlled, one of the horizontal EPROM gate conductors, e.g. Conductor 16, 18 or 20, selects and applies an EPROM read voltage to all memory cells which are connected to the respective X line work together. The Y selection circuit receives in a corresponding manner 14 takes an input from a suitable Y-line decoder and pre-charges one of several vertical lines, for example lines 22, 24, 26 or 28. Those at the intersection of the selected X line and the selected Y-line arranged memory cell is then queried by the read signal, and a state of the line or the non-conduction, which represents a binary on / off state, can be achieved by an output buffer amplifier, for example amplifier 30, can be determined.

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EPROM cells arranged on integrated circuit chips are usually designed as double-gate transistors, for example transistor 38 at the interface of Y-line 22 and X-line 16 "The double-gate transistor is a silicon MOS transistor, which is a floating ( floating) gate element which is arranged between the n-channel and the control gate element and insulated from them. This central or floating gate affects the conductivity of the transistor only to a small extent, as long as it is not ensured that it contains an electron charge. Therefore, in order to program an EPROM transistor, a voltage which is higher than the normal operating voltage is applied to the gate and drain elements, so that the floating gate element discharges a small electron charge . sorbs and holds. This floating gate charge increases the conduction threshold of the control gate transistor from a low level of about 2 volts to a level of 10 volts or higher, depending on the amount of charge being drawn. An EPROM matrix which contains several charged and uncharged double-gate transistors can therefore be read by applying a read voltage which is at least equal to the threshold voltage of an unprogrammed or uncharged transistor, but still definitely below the threshold level of a charged or uncharged transistor. programmed transistor. .

As described above, it has been impossible, EPROM, such as _e described double gate transistor cell array to be placed on circuit die, where there is a negative substrate. The reason for this is that the bias would increase the threshold voltage of the EPROM transistor significantly, namely by variable amounts, depending on the variable level of the substrate bias . The circuit shown in FIG measures the threshold voltage of an unprogrammed EPROM test transistor,

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which is located on the same substrate and is subjected to the same substrate bias. The reference generator 40 therefore generates a DC output reference voltage which is equal to the threshold voltage of the unprogrammed EPROM transistor and, accordingly, of all other unprogrammed EPROM transistors which are located on the same semiconductor die and are subjected to the same substrate bias. The high-voltage generator 42 receives this reference voltage and it increases this voltage by a fixed level of z, B ₀ 2.5 volts in order to increase the access speed of the memory to a level of approximately 200 nanoseconds »The conductor 44 at the output of the high-voltage generator 42 is connected to the drain electrodes of several gate transistors, e.g. 46, 48 and 50, and the gates of these transistors are connected to the horizontal X-lines of the matrix 10 via light-depletion transistors, which will be described below. The source elements of these transistors are directly connected to connected to the control gates of the EPROM transistors in the line assigned to them and the control gates of the transistors 46, 48 and 50 are connected to the corresponding X lines at the output of the X selection circuit 12.

Fig '2 shows schematically details of the reference generator and the high-voltage generator 42 _S which are contained in Figure "1 in block diagram ₀ The drawing of FIG. 2 includes transistors and various inverter circuits, which are shown with different symbols" These various circuits are for convenience of Dar ~ position and the explanation in Fig. 3 reproduced.

FIGS. 3A to 3D show the various ones contained in FIG Inverter circuits. In Fig. 3A, the symbol for an inverter includes a small triangle »The equivalent schematic

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Representation "is located directly below the inverter symbol, and it includes a light depletion stress transistor 52 connected between V "_ and the output terminal

CC

lies. The gate element of transistor 52 is connected to the output terminal and coupled to the drain of a transistor 53, whose source is at ground reference potential and whose gate forms the input of the circuit.

FIG. 3B shows a representation like the circuit of FIG. 3A, with the difference that the fully marked triangle within the inverter symbol represents a severe depletion load, so that depletion transistor 54 is always in the on-state is located; according to this illustration there is no voltage drop between V_. and the output terminal.

CC

3C shows an inverter symbol in which the letter ¹¹ E "is located. This shows an enhancement transistor 56 which lies between V _ and the output, the

CC

Gate of transistor 56 coupled to current source V

CC

is. Transistor 56 is therefore always in the on state, but it carries a]
and the exit.

however, it leads to a threshold voltage drop between V "_

CC

Fig «3D shows the symbol for a gate whose high resp. low output is controlled by inputs A or "B, as the accompanying schematic drawing shows. Transistor 58 as shown in FIG. 3D may be an enhancement circuit labeled "E", a light depletion stress transistor with the open triangle or a heavy depletion transistor with the filled triangle be.

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The description of the schematic drawing according to FIG. 2 is now continued. The reference generator within FIG Dashed line 40 contains one or more unprogrammed or uncharged EPROM transistors 60, 62, which lie between circuit point 64 and ground reference potential » As a reference voltage control transistor to be described below 88 requires a gate voltage which is substantially higher than the voltage applied to the circuit V is a voltage pumping circuit provided on

Potential V of preferably 5 volts is applied to terminal 66 j and then it is raised to a higher voltage of etv / a 7.5 volts by the voltage pumping circuit with in series switched transistors 68, 70 and 72 brought the gate and drain of the transistor 68 are connected to each other, and the source element is coupled to the gate and drain of transistor 70. The gate of transistor 70 is The source of the transistor is also capacitively coupled to one phase of the associated two-phase computer clock circuit is coupled to the gate and drain of transistor 72, the gate element of which is coupled to the second phase of the two-phase clock circuit is capacitively coupled. The pumping effect achieved by the two clock phases generates a high-frequency half-wave direct current signal above the V "base potential,

CC

and this half-wave signal is passed through a condenser 74 which is located between the ground reference potential and the source element of transistor 72 _s filtered "Turning now to the source of transistor 72 occurring voltage is considerably higher than the voltage V""and it is preferably 7 _S 5 Voit ₀

C C

To ensure that when starting up the circuit faster service is available, the reference contains = generator preferably a start-up circuit with transistor 76 »which between the V terminal and conductor

CC

liegte The gate of transistor 76 is coupled to the output of an inverter 80 whose input is from node 64, so that _s if the potential of the circuitry

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Point 64 is at zero level, the inverter 80 on applies positive signal to the gate of transistor 76; the potential V ,, _ is therefore at the beginning on conductor 78.

cc

closing when node 64 assumes a potential, inverter 80 will place transistor 76 in the off state.

The source element of transistor 72 in the voltage pumping circuit carries the higher voltage across conductor 82 to a heavy depletion stress transistor 84 located between conductors 82 and 78. The gate element of the transistor is coupled to conductor 78 so that transistor 84 has a variable resistance depending on the voltage level on conductor 78. Conductor 78 is coupled to node 64 via an enhancement transistor 86, the gate element of which is coupled to conductor 78. Transistor 86 is therefore always in the on state and it introduces a small voltage drop which is equal to its threshold voltage. The voltage between node 64 and ground reference potential is determined by the threshold voltage of EPROM transistor 60 or 62. There is therefore a voltage divider circuit between the high-voltage conductor 82 and ground potential, which contains a series resistance of transistor 84, the threshold value of enhancement transistor 86 and the threshold value of EPROM transistor 60 or 62, and node 64 will always be at a level which is the same is the threshold of an unprogrammed EPROM transistor.

Conductor 78 will be at a level equal to the threshold of the EPROM transistor plus the threshold of the enhancement transistor 86 is «, conductor 78 is with connected to the gate electrode of an enhancement transistor 88, whose source element is connected to the V _ "terminal 66.

CC

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The voltage j which is present at the drain element of the transistor occurs, will be equal to the voltage applied to its gate ρ minus the threshold voltage of transistor 88. Since conductor 78 is at a potential equal to the threshold value of EPROM transistor 60 or 62 plus the threshold voltage of transistor 86 was “the voltage at the output of transistor 88 be a voltage threshold lower than the voltage appearing on conductor 78, or it will be exactly equal to the voltage threshold of the unprogrammed EPROM transistor 60 or 62.

In the schematic drawing of the reference generator 40 there is a pair of transistors 90 connected in series and 92p which with EPROM transistors 60 or 62 in parallel are connected and .between circuit point 64 and ground potential »These transistors are double-gate transistors however, like EPROM transistors 60 and 62 j they are designed so that the two gates within each transistor are interconnected so that their respective threshold voltages are about half that of the Floating gate EPROM transistors 60 and 62. The purpose of the series transistors 90 and 92 is to im to provide essentially the same voltage threshold value at node 64 if the two EPROM transistors 60 and 62 should be programmed in some way and not the desired EPROM threshold voltage at circuit point 64 available »The transistors 90 and 92 are therefore for the actual operation of the Circuitry is not required, but according to a preferred embodiment they are with an auxiliary function intended as a security group «,

The output of the reference generator 4u carries a voltage which is exactly equal to the threshold voltage of an unprogrammed EPROM transistor as described above.

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ORIGINAL INSPECTED

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When this voltage level is applied to the EPROM transistors in the Matrix .10 according to FIG. 1 were created, the unprogrammed Memory transistors provide an output, but the access time of the memory would be of the order of magnitude of hours. In order to set this access time to a technically usable value, it is necessary to use the read or Raising EPROM transistor gate voltage above the threshold level of the unprogrammed EPROM transistors «If the Reading voltage would be unnecessarily high, the programmed EPROM transistors can deliver a false output, and even if the read voltage is lowered appropriately to avoid such an erroneous output, it would Reading the matrix with a higher voltage than it is necessary, over time, will destroy the program. Therefore a must more precise, predetermined voltage level above the unprogrammed threshold voltage can be generated. As already described, this higher read voltage controls the access speed of the memory, and it has been found that a read voltage of 2.5 volts plus the EPROM threshold voltage is required to obtain an access time of approximately 200 nanoseconds. If access times for slower access are desired, the mentioned higher voltage values can do a bit be reduced.

The EPROM transistor threshold reference voltage generated in the reference generator 40 is applied to the high-voltage generator 42, and it is switched here by a gate transistor 96, the drain electrode of which is connected to the output conductor 44, which is connected to the source electrodes of all of the X-choice gate transistors is in connection, for example transistor 46, which is described in connection with FIG became. The drain electrode of transistor 96 is also connected to ground reference potential via a gate transistor 98, and the control gate of transistor 98 is coupled to input terminal 100 which has an active low read phase

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signal from the associated computer circuit is applied » Thus, until the read ground signal is applied to input terminal 100, transistor 98 is "on" to ground 44p and when the read phase signal is applied becomes transistor 98 switched to the "off" state, so that conductor 44 is disconnected from ground.

For a better understanding of the circuit of the high-voltage generator 42 according to FIG. 2, time-voltage curves are shown in FIG. 4, which show signals which occur at different points in the circuit, which are designated by the corresponding letters. Curve A in Fig. 4 shows the directed towards the earth read phase signal, which is connected to terminal 100 as shown in Fig. Z. The signal is applied to the gate of transistor 98 to render it non-conductive, and it is also applied to one input terminal of a NOR gate 102 which produced a low output prior to the application of the grounded signal, which was applied to the gate of transistor 96 via transistor 104. The gate of transistor 104 is directly coupled to the V_ source so that a high voltage is present and transistor 96 is placed fully on.

The read phase signal applied to terminal 100 is also sent through a delay circuit which is a heavy depletion inverter 106 in series with an RC circuit in which there is transistor 108, the gate of which to his Input is fed back so that it represents a resistance; the RC circuit also includes a grounded one Capacitor 110. The output from this RC delay line is represented by curve B in Fig. 4 which is normally at a low level; she will be about 250 nanoseconds after the grounding signal at the terminal 100 is applied, raised to its high level «, the delay line also includes an enrichment inverter 112,

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its output voltage level is controlled by the signal output of the transistor 1OS in accordance with curve B in FIG will. The output of transistor 112 is therefore represented by the same signal B of FIG. 4, and this Signal is applied to the second input terminal of NOR gate 102 so that a signal is generated at its output which is represented by curve C of FIG is. The transistor 96 in the high-voltage generator circuit is therefore set in the on ^ state according to curve C only for a period of about 250 nanoseconds.

The output of inverter 112 is applied to the input of a light stress depletion inverter 114, which receives its second input from terminal 100. When input B to inverter 114 is high, its output is grounded and when the input goes low the inverter is enabled to signal A at To include terminal 100 “The result is a signal which represented by curve D in Fig. 4; it is applied to the input of inverter 116. Shunted to inverter 116 is a circuit which includes an inverter 118 and a transistor 120; the gate element of the transistor 120 is coupled to the power source V so that its

CC

Output drain a full V_ signal to control inverter 116

CC

which generates an output signal represented by curve E. is shown in FIG.

The output signal from inverter 116 is applied to one side of a capacitor 122, the other terminal of which is connected to the conductor and the drain electrode of the gate transistor 96. As already described, application of the read phase signal to terminal 100 places transistor 96 in the on state, while transistor 98 is placed in the off state. About 250 nanoseconds later, transistor is set to the off state while transistor 98 remains in the off state. As curve F in Fig. 4 shows, this becomes

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Applied output of the inverter 116 to capacitor 122 in the one moment staggered in the transistor 96 in the off state _o is This has the result that the voltage on conductor 44 increases by a value corresponding to the ratio of the capacitance of the capacitor 122 of the total circuit capacity 124 in a selected X line of the EPROM matrix 10 ._ is. Capacitor 122 is therefore carefully selected so that its capacitance is equal to the total X-line circuit capacitance 124. The signal appearing at point F in the circuit is therefore represented by "curve F of FIG. 4; its first step shows the threshold voltage of the EPROM transistor, while the second, rounded step corresponds to half the value of V__. It can be seen that the voltage drops back to its low level when the read signal at terminal 100 and, accordingly, the line through transistor 98 to ground is interrupted.

The EPROM gate or read voltage applied to conductor 44 is now passed through gate transistor 46 to the control gate of the selected EPROM transistor. When the X selection circuit 12 has selected the X line 16, the 5 volt signal becomes V.

O - CC

from circuit 12 (curve G in FIG. 4) through a light depletion transistor 126 is applied to the gate of transistor 46. The gate of transistor 126 is coupled to V “, and

CC

the gate of the transistor 46 is the full voltage V on-

CC

to take. If the high-voltage generator 42 then supplies an output to the conductor 44, part of this becomes higher Voltage capacitively coupled to the gate of transistor 46 as shown by capacitor 128 shown in phantom which represents the capacitance present within the circuit. This will reduce the gate voltage of

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Transistor 46 an additional amount over its normal level V "_ corresponding to the representation of curve H increased in Fig. 4. This additional amount is the ratio of the capacity of 128 to the sum of the capacities of 128 and 130 (between the gate of transistor 46 and ground) proportional. The transistor 46, which now has a high Gate voltage is fully "on" and will apply the required high read voltage to the gates of those EPROM transistors which are connected to the X-line 16 are connected; this is also shown by curve J in FIG. 4.

The invention advantageously enables the representation a circuit on the semiconductor chip - an integrated MOS circuit with a CPU (central processing unit) and an EPROM, where the correct EPROM read voltage is independent of the Substrate bias of the CPU is generated. This is achieved in that the circuit has a voltage reference generator which continuously contains a double gate EPROM transistor measures and provides a reference voltage which is exactly equal to its threshold voltage, and a controlled High-voltage generator, which increases the reference voltage by a fixed value in order to achieve an optimal access time and gate voltage of the EPROM.

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Claims (1)

Expectations (\ J Circuit for generating a read voltage for double-gate EPROM transistors in a memory circuit with substrate bias, characterized by a reference voltage generator circuit for measuring the threshold voltage of an unprogrammed EPROM pattern transistor in the Generator circuit with applied substrate bias, and for generating a reference output voltage which is equal to the Threshold voltage is a high-voltage generator, which is connected to the reference voltage generator circuit is coupled and responsive to the reference output voltage to produce an output signal which is equal to the threshold voltage plus a predetermined constant additional voltage, and a gate transistor, which is between the output of the high-voltage generator and each one of a plurality of EPROM transistor gate conductors is coupled, wherein the gate electrode of the gate transistor is coupled to the output of an X selection circuit cooperating with the memory. 030047/0888 - 2 - 'F 8055 2. Circuit according to claim 1, characterized in that that the total output voltage generated by the high-voltage generator higher than the threshold voltage of an unprogrammed EPROM transistor and lower than the threshold voltage of the programmed EPROM transistor. 3. Circuit according to Claim 2, characterized in that the high-voltage generator is controlled by an external read pulse with a first pulse duration and has a delay circuit which converts the reference voltage received from a reference voltage generator circuit to a pulse of a second duration which is shorter than the The duration of the first pulse is limited. 4. Circuit according to claim 3, characterized in that that the high-voltage generator contains a capacitor, which between the output conductor of the generator and the output of the Delay circuit is and is charged to a first level by the reference voltage pulse of a second duration, wherein the delay circuit on termination of the pulse with a first duration the capacitor with an additional charge provides. 5. Circuit according to claim 4, characterized in that the additional charge reaches a total amplitude which of the supply voltage V "times the ratio of the capacitance cc of the capacitor is proportional to the circuit capacitance of the output conductor of the high-voltage generator. 6. Circuit according to one of claims 1-5, characterized in that the reference voltage generator circuit at least one unprogrammed double gate EPROM transistor contains. 030047/0888 - 3 - F 8055 7θ circuit according to claim 6, characterized by at least two series-connected non-programmable double-gate transistors in parallel with the EPROM transistor, which provide essentially the same threshold voltage measurement of the EPROM transistor. 8. A circuit according to claim 6, characterized in that the output reference voltage of the reference voltage generator circuit is controlled by a control transistor, which is connected between the supply voltage V "_ and" the output conductor of the CC - Reference generator is, wherein the voltage control electrode of the control transistor is coupled to the EPROM transistor and responsive to the threshold voltage of the EPROM transistor such that it corresponds to the output level of the reference voltage generating circuit to the voltage level of its voltage control electrode minus the threshold voltage of the control transistor controls. 9. A circuit according to claim 8, characterized in that the EPROM transistor with a first transistor in series whose threshold voltage is equal to the threshold voltage of the control transistor to the measured EPROM transistor threshold voltage by an amount equal to the threshold voltage drop through the control transistor is, so that the control transistor provides an output voltage which is exactly equal to the threshold voltage of the EPROM transistor is. 10. A circuit according to claim 9, characterized in that the reference voltage generator circuit is a voltage pump circuit to raise the amplitude of the voltage above the level V of the circuit, the raised level CC is applied through the first series transistor and the EPROM transistor and to the control electrode of the control transistor is present. 030047/0888 / - 4 - F 8055 11. Circuit according to claim 10, characterized in that that the reference voltage generator circuit is a start-up circuit which is responsive to a low output of the voltage pump circuit such that it has a Voltage level V__ directly to the control electrode of the CC Control transistor applies. 12. Circuit according to claim §, characterized in that that the control gate of the gate transistor is coupled to the output of the X selection circuit via a transistor whose Gate is at voltage level V _. CC 13. Circuit according to claim 12, characterized in that that the voltage level on the control gate of the gate transistor is increased above the level V__ by an amount which is proportional CC - _fc tional the output level of the high-voltage generator circuit and the source-to-gate capacitance of the gate transistor, and inversely proportional to the sum of the source-to-gate capacitance and the gate-to-earth capacitance is. 030047/0888