IT8067601A0 - Circuito di tensione di lettura per memorie cancellabili e programmabili a sola lettura - Google Patents

Circuito di tensione di lettura per memorie cancellabili e programmabili a sola lettura

Info

Publication number
IT8067601A0
IT8067601A0 IT8067601A IT6760180A IT8067601A0 IT 8067601 A0 IT8067601 A0 IT 8067601A0 IT 8067601 A IT8067601 A IT 8067601A IT 6760180 A IT6760180 A IT 6760180A IT 8067601 A0 IT8067601 A0 IT 8067601A0
Authority
IT
Italy
Prior art keywords
erasable
memories
programmable read
voltage circuit
reading voltage
Prior art date
Application number
IT8067601A
Other languages
English (en)
Other versions
IT1129217B (it
Inventor
Rajesh Haribhgi Parekh
Original Assignee
Fairchild Camera Instr Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera Instr Co filed Critical Fairchild Camera Instr Co
Publication of IT8067601A0 publication Critical patent/IT8067601A0/it
Application granted granted Critical
Publication of IT1129217B publication Critical patent/IT1129217B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
IT67601/80A 1979-05-14 1980-04-17 Circuito di tensione di lettura per memorie cancellabili e programmabili a sola lettura IT1129217B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US3861279A 1979-05-14 1979-05-14

Publications (2)

Publication Number Publication Date
IT8067601A0 true IT8067601A0 (it) 1980-04-17
IT1129217B IT1129217B (it) 1986-06-04

Family

ID=21900899

Family Applications (1)

Application Number Title Priority Date Filing Date
IT67601/80A IT1129217B (it) 1979-05-14 1980-04-17 Circuito di tensione di lettura per memorie cancellabili e programmabili a sola lettura

Country Status (5)

Country Link
JP (1) JPS59917B2 (it)
DE (1) DE3017960C2 (it)
FR (1) FR2456991B1 (it)
GB (1) GB2049327B (it)
IT (1) IT1129217B (it)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5693363A (en) * 1979-12-04 1981-07-28 Fujitsu Ltd Semiconductor memory
DE3279855D1 (en) * 1981-12-29 1989-09-07 Fujitsu Ltd Nonvolatile semiconductor memory circuit
EP0189594B1 (en) * 1984-12-28 1992-08-12 Nec Corporation Non-volatile semiconductor memory device
JPS63149534A (ja) * 1986-12-13 1988-06-22 Hokutou Koki Kogyo Kk 重心検出器
US5877981A (en) * 1987-06-29 1999-03-02 Kabushiki Kaisha Toshiba Nonvolatile semiconductor memory device having a matrix of memory cells
US6034899A (en) * 1987-06-29 2000-03-07 Kabushiki Kaisha Toshiba Memory cell of nonvolatile semiconductor memory device
US6545913B2 (en) 1987-06-29 2003-04-08 Kabushiki Kaisha Toshiba Memory cell of nonvolatile semiconductor memory device
US5448517A (en) * 1987-06-29 1995-09-05 Kabushiki Kaisha Toshiba Electrically programmable nonvolatile semiconductor memory device with NAND cell structure
JP3109736B2 (ja) * 1987-07-31 2000-11-20 株式会社東芝 半導体集積回路と浮遊ゲート型メモリセルの読み出し駆動方法

Also Published As

Publication number Publication date
FR2456991B1 (fr) 1985-11-22
IT1129217B (it) 1986-06-04
FR2456991A1 (fr) 1980-12-12
JPS55153195A (en) 1980-11-28
GB2049327B (en) 1983-03-30
DE3017960A1 (de) 1980-11-20
GB2049327A (en) 1980-12-17
JPS59917B2 (ja) 1984-01-09
DE3017960C2 (de) 1984-08-30

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