IT1071999B - Dispositivo di memoria programmabile a sola lettura e procedimento perla sua fabbricazione - Google Patents
Dispositivo di memoria programmabile a sola lettura e procedimento perla sua fabbricazioneInfo
- Publication number
- IT1071999B IT1071999B IT70128/76A IT7012876A IT1071999B IT 1071999 B IT1071999 B IT 1071999B IT 70128/76 A IT70128/76 A IT 70128/76A IT 7012876 A IT7012876 A IT 7012876A IT 1071999 B IT1071999 B IT 1071999B
- Authority
- IT
- Italy
- Prior art keywords
- reading
- procedure
- manufacture
- memory device
- programmable memory
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7886—Hot carrier produced by avalanche breakdown of a PN junction, e.g. FAMOS
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0416—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
- G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
- G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
- G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0705—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type
- H01L27/0727—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors
- H01L27/0733—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common comprising components of the field effect type in combination with diodes, or capacitors or resistors in combination with capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/05—Making the transistor
- H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
- H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/168—V-Grooves
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/927—Different doping levels in different parts of PN junction to produce shaped depletion layer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Non-Volatile Memory (AREA)
- Read Only Memory (AREA)
- Semiconductor Memories (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US05/683,185 US4222062A (en) | 1976-05-04 | 1976-05-04 | VMOS Floating gate memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
IT1071999B true IT1071999B (it) | 1985-04-10 |
Family
ID=24742907
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT70128/76A IT1071999B (it) | 1976-05-04 | 1976-12-29 | Dispositivo di memoria programmabile a sola lettura e procedimento perla sua fabbricazione |
Country Status (6)
Country | Link |
---|---|
US (1) | US4222062A (it) |
JP (1) | JPS52134338A (it) |
DE (1) | DE2654728B2 (it) |
GB (1) | GB1525681A (it) |
IT (1) | IT1071999B (it) |
NL (1) | NL7700965A (it) |
Families Citing this family (53)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4252579A (en) * | 1979-05-07 | 1981-02-24 | International Business Machines Corporation | Method for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline deposition |
WO1981002222A1 (en) * | 1980-01-21 | 1981-08-06 | Mostek Corp | Composit gate interconnect structure |
JPS56126969A (en) * | 1980-03-11 | 1981-10-05 | Toshiba Corp | Integrated circuit device |
US4353086A (en) * | 1980-05-07 | 1982-10-05 | Bell Telephone Laboratories, Incorporated | Silicon integrated circuits |
USRE32090E (en) * | 1980-05-07 | 1986-03-04 | At&T Bell Laboratories | Silicon integrated circuits |
NL8002635A (nl) * | 1980-05-08 | 1981-12-01 | Philips Nv | Programmeerbare halfgeleiderinrichting en werkwijze ter vervaardiging daarvan. |
US4326332A (en) * | 1980-07-28 | 1982-04-27 | International Business Machines Corp. | Method of making a high density V-MOS memory array |
EP0048610B1 (en) * | 1980-09-22 | 1986-01-15 | Kabushiki Kaisha Toshiba | Semiconductor device and its manufacture |
US4407058A (en) * | 1981-05-22 | 1983-10-04 | International Business Machines Corporation | Method of making dense vertical FET's |
JPS6059677B2 (ja) * | 1981-08-19 | 1985-12-26 | 富士通株式会社 | 半導体記憶装置 |
JPS6135554A (ja) * | 1984-07-28 | 1986-02-20 | Nippon Telegr & Teleph Corp <Ntt> | 読出し専用メモリ−およびその製造方法 |
US4763177A (en) * | 1985-02-19 | 1988-08-09 | Texas Instruments Incorporated | Read only memory with improved channel length isolation and method of forming |
US4713677A (en) * | 1985-02-28 | 1987-12-15 | Texas Instruments Incorporated | Electrically erasable programmable read only memory cell including trench capacitor |
US5017977A (en) * | 1985-03-26 | 1991-05-21 | Texas Instruments Incorporated | Dual EPROM cells on trench walls with virtual ground buried bit lines |
US5135879A (en) * | 1985-03-26 | 1992-08-04 | Texas Instruments Incorporated | Method of fabricating a high density EPROM cell on a trench wall |
JPS61280651A (ja) * | 1985-05-24 | 1986-12-11 | Fujitsu Ltd | 半導体記憶装置 |
US4811067A (en) * | 1986-05-02 | 1989-03-07 | International Business Machines Corporation | High density vertically structured memory |
US4769786A (en) * | 1986-07-15 | 1988-09-06 | International Business Machines Corporation | Two square memory cells |
USRE33972E (en) * | 1986-07-15 | 1992-06-23 | International Business Machines Corporation | Two square memory cells |
US4874715A (en) * | 1987-05-20 | 1989-10-17 | Texas Instruments Incorporated | Read only memory with improved channel length control and method of forming |
JPH021988A (ja) * | 1987-12-03 | 1990-01-08 | Texas Instr Inc <Ti> | 電気的にプログラム可能なメモリ・セル |
US4979004A (en) * | 1988-01-29 | 1990-12-18 | Texas Instruments Incorporated | Floating gate memory cell and device |
US5016068A (en) * | 1988-04-15 | 1991-05-14 | Texas Instruments Incorporated | Vertical floating-gate transistor |
US5027319A (en) * | 1988-09-02 | 1991-06-25 | Motorola, Inc. | Gate array macro cell |
US5045490A (en) * | 1990-01-23 | 1991-09-03 | Texas Instruments Incorporated | Method of making a pleated floating gate trench EPROM |
US5053839A (en) * | 1990-01-23 | 1991-10-01 | Texas Instruments Incorporated | Floating gate memory cell and device |
US5049515A (en) * | 1990-03-09 | 1991-09-17 | Intel Corporation, Inc. | Method of making a three-dimensional memory cell with integral select transistor |
US5071782A (en) * | 1990-06-28 | 1991-12-10 | Texas Instruments Incorporated | Vertical memory cell array and method of fabrication |
US5430673A (en) * | 1993-07-14 | 1995-07-04 | United Microelectronics Corp. | Buried bit line ROM with low bit line resistance |
US5563823A (en) * | 1993-08-31 | 1996-10-08 | Macronix International Co., Ltd. | Fast FLASH EPROM programming and pre-programming circuit design |
JP3159850B2 (ja) * | 1993-11-08 | 2001-04-23 | シャープ株式会社 | 不揮発性半導体記憶装置及びその製造方法 |
US5501996A (en) * | 1994-12-14 | 1996-03-26 | United Microelectronics Corporation | Method of manufacture of high coupling ratio single polysilicon floating gate EPROM or EEPROM cell |
US5930171A (en) * | 1995-05-22 | 1999-07-27 | Siemens Aktiengesellschaft | Constant-current source with an EEPROM cell |
US5854501A (en) * | 1995-11-20 | 1998-12-29 | Micron Technology, Inc. | Floating gate semiconductor device having a portion formed with a recess |
US5898202A (en) * | 1996-12-03 | 1999-04-27 | Advanced Micro Devices, Inc. | Selective spacer formation for optimized silicon area reduction |
US5926714A (en) * | 1996-12-03 | 1999-07-20 | Advanced Micro Devices, Inc. | Detached drain MOSFET |
US6020232A (en) * | 1996-12-03 | 2000-02-01 | Advanced Micro Devices, Inc. | Process of fabricating transistors having source and drain regions laterally displaced from the transistors gate |
US5900666A (en) * | 1996-12-03 | 1999-05-04 | Advanced Micro Devices, Inc. | Ultra-short transistor fabrication scheme for enhanced reliability |
US6063664A (en) * | 1998-03-27 | 2000-05-16 | Taiwan Semiconductor Manufacturing Company | Method of making EEPROM with trenched structure |
US6124610A (en) * | 1998-06-26 | 2000-09-26 | Advanced Micro Devices, Inc. | Isotropically etching sidewall spacers to be used for both an NMOS source/drain implant and a PMOS LDD implant |
US6236082B1 (en) | 1998-08-13 | 2001-05-22 | National Semiconductor Corporation | Floating gate semiconductor device with reduced erase voltage |
US6657261B2 (en) | 2001-01-09 | 2003-12-02 | International Business Machines Corporation | Ground-plane device with back oxide topography |
US6432754B1 (en) | 2001-02-20 | 2002-08-13 | International Business Machines Corporation | Double SOI device with recess etch and epitaxy |
US6473940B1 (en) * | 2001-06-29 | 2002-11-05 | Harsco Technologies Corporation | Knob for a post valve |
US20090130826A1 (en) * | 2004-10-11 | 2009-05-21 | Samsung Electronics Co., Ltd. | Method of Forming a Semiconductor Device Having a Strained Silicon Layer on a Silicon-Germanium Layer |
KR100593747B1 (ko) * | 2004-10-11 | 2006-06-28 | 삼성전자주식회사 | 실리콘게르마늄층을 구비하는 반도체 구조물 및 그 제조방법 |
TWI288473B (en) * | 2005-10-05 | 2007-10-11 | Promos Technologies Inc | Flash memory structure and method for fabricating the same |
US10038004B2 (en) | 2009-06-22 | 2018-07-31 | Cypress Semiconductor Corporation | NAND memory cell string having a stacked select gate structure and process for for forming same |
US20100322006A1 (en) * | 2009-06-22 | 2010-12-23 | Ming Sang Kwan | Nand memory cell string having a stacked select gate structure and process for for forming same |
US9691898B2 (en) * | 2013-12-19 | 2017-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Germanium profile for channel strain |
US9287398B2 (en) | 2014-02-14 | 2016-03-15 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor strain-inducing scheme |
US11189623B2 (en) * | 2018-12-18 | 2021-11-30 | Micron Technology, Inc. | Apparatuses, memory devices, and electronic systems |
KR20220004845A (ko) * | 2020-07-02 | 2022-01-12 | 삼성디스플레이 주식회사 | 표시 장치 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS525233B2 (it) * | 1972-02-29 | 1977-02-10 | ||
US3975221A (en) * | 1973-08-29 | 1976-08-17 | American Micro-Systems, Inc. | Low capacitance V groove MOS NOR gate and method of manufacture |
US3992701A (en) * | 1975-04-10 | 1976-11-16 | International Business Machines Corporation | Non-volatile memory cell and array using substrate current |
-
1976
- 1976-05-04 US US05/683,185 patent/US4222062A/en not_active Expired - Lifetime
- 1976-12-02 DE DE2654728A patent/DE2654728B2/de not_active Ceased
- 1976-12-29 IT IT70128/76A patent/IT1071999B/it active
-
1977
- 1977-01-19 GB GB2191/77A patent/GB1525681A/en not_active Expired
- 1977-01-31 NL NL7700965A patent/NL7700965A/xx not_active Application Discontinuation
- 1977-05-02 JP JP5005677A patent/JPS52134338A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
DE2654728A1 (de) | 1977-11-10 |
NL7700965A (nl) | 1977-11-08 |
GB1525681A (en) | 1978-09-20 |
US4222062A (en) | 1980-09-09 |
DE2654728B2 (de) | 1978-04-13 |
JPS52134338A (en) | 1977-11-10 |
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