WO1981002222A1 - Composit gate interconnect structure - Google Patents

Composit gate interconnect structure Download PDF

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Publication number
WO1981002222A1
WO1981002222A1 PCT/US1980/000652 US8000652W WO8102222A1 WO 1981002222 A1 WO1981002222 A1 WO 1981002222A1 US 8000652 W US8000652 W US 8000652W WO 8102222 A1 WO8102222 A1 WO 8102222A1
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WO
WIPO (PCT)
Prior art keywords
layer
polycrystalline silicon
integrated circuit
substrate
gate
Prior art date
Application number
PCT/US1980/000652
Other languages
French (fr)
Inventor
W Gosney
T Chan
Original Assignee
Mostek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mostek Corp filed Critical Mostek Corp
Priority to AU62234/80A priority Critical patent/AU6223480A/en
Publication of WO1981002222A1 publication Critical patent/WO1981002222A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
    • H01L21/76889—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances by forming silicides of refractory metals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53271—Conductive materials containing semiconductor material, e.g. polysilicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/495—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a simple metal, e.g. W, Mo
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the eomposit gate structure including the polycrystalline silico layer and the refractory metal layer exhibits the best properties of eac component.
  • the polycrystalline silicon has relatively low conductivit (1 x 10 ohm-cm), it is capable of withstanding the MOS processing condition
  • the refractory metal for example molybdenum, has a relatively hig conductivity (1 x 10 , ohm-cm), but is difficult to process when exposed to th chemical and oxidizing reagents at high temperatures.
  • the eomposit structur on the other hand, has the high melting point, high oxidation resistance an pattern definition capability of polycrystalline silicon alone, and importantl has the substantially lower resistivity of the refractory metal.
  • the eomposi gate/interconnect structure is, therefore, highly compatible with the silico gate processes and is suitable as a gate material for constructing high spee MOS devices.
  • the self-aligned gate structure provided by using the interleave molybdenum/polycrystalline silicon gate strips as the etching mask for removin the oxide layer reduces capacitance and thus significantly increases the spee of operation of the circuit.
  • the interleaved molybdenum/polycrystalline silico layers 26, 28 can also be used as a eomposit interconnecting conductor 36, an thus can provide a third layer of interconnection to increase the functiona density of the integrated circuit.
  • the interconnect structure shown in FIGURE 16 is produced b similar steps, except that the first layer is formed by depositing a film o polycrystalline silicon 28 over the oxide layer 12, followed by the deposition of molybdenum layer 26, with a final layer of polycrystalline silicon deposited ove the molybdenum layer 26.
  • This structure is extremely stable and is highl compatible with MOS processing conditions.
  • the molybdenum metal layer is protected by the polycrystalline silico layer 28, which serves as a shield against the reagents of the MOS processin steps, and can be easily oxidized.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

A composit gate/interconnect structure (36) is formed by interleaved layers of polycrystalline silicon (28) and a refractory metal (26) selected from the group consisting of molybdenum, tungsten, platinum and titanium. The combination of a refractory metal such as molybdenum with polycrystalline silicon produces a stable gate material having low resistivity which can be formed by simple fabrication processes in the construction of high speed MOS devices.

Description

COMPOSIT GATE INTERCONNECT STRUCTURE
BACKGROUND OF THE INVENTION Field of the Invention:
The present invention is generally related to LSI technology, and more particularly relates to an improved gate/interconnect structure for MOS integrated circuits of the type implemented on a semiconductor substrate. Description of the Prior Art:
Large scale integration (LSI) techniques have brought about the construction of large arrays of binary storage elements on a single chip of silicon. These storage cells, typically using MOS technology, consist of multi- component circuits in a conventional bi-stable arrangement. The immediate advantages of such semiconductor storage devices are the high packing density and low power requirements. The insulated gate MOS transistor has served well in this application area since it requires less substrate area (thereby increasing the packing density) and operates at very low power levels.
MOS field effect transistors are commonly used in the construction of integrated circuits such as the read only memory (ROM). An important ROM performance characteristic is access time, which is defined as the time required or a data output node to change from a logic low to a logic high level. In the typical MOS ROM, access time is a function of supply current and the distributed resistance of interconnect lines such as address and word lines, and device gate lines. Signal propagation through the ROM is therefore limited by the distributed resistance of the interconnection lines, and a further improvement in ROM access time can be achieved by reducing the resistivity of the interconnection lines.
Scaling theory indicates that circuit performance for such devic improves as physical sizes are scaled down. However, one circuit paramet which does not improve is the distributed, series sheet resistance of t polycrystalline silicon interconnects. As the sizes are reduced, the resistan of the interconnect circuit increases. Therefore it is to be expected that t parasitic resistances imposed by the polycrystalline silicon interconnects wi cause degraded performance of MOS devices due to the corresponding increas signal propagation delays and increased access times as the interconnect widt are reduced. The RC circuit time constant will remain fairly constant as t device is scaled down. What will change is the ratio of the memory cycle tim to the RC time constant, which ratio will become smaller unless the she resistance is reduced. Therefore, as cycle times become less than 100 ns, R time constant delays will increase substantially, in the range of 20-30 ns. The distributed sheet resistance is due primarily to the volume the deposited polycrystalline silicon film as opposed to the effect of t monocrystalline silicon substrate. Mobility in the polycrystalline silic material is one-half to one- third that of the monocrystalline silicon substrat Assuming comparable film thickness and junction depth, the polycrystallin silicon resistance/square will be from two to three times that of t monocrystalline silicon substrate, due to the lower mobility caused by grai boundaries.
Further increases in doping are not believed to be useful, sinc doping is already at near solid-solubility limits. Although alternate gate materials such as the refractory meta have a lower resistivity, they are subject to "peeling" degradation as a result the high temperatures associated with oxide layer deposition. Further, th refractory metals are subject to corrosion. For example, molybdenum wi react with phosphorus in the passivating films in the presence of any residu moisture, thereby forming phosphoric acid and other corrosive product Additionally, it is difficult to adhere such metals directly to th monocrystalline silicon substrate. SUMMARY OF OBJECTS OF THE INVENTION
It is, therefore, the principal object of the present invention to provide a gate/interconnect structure having a relatively low sheet resistance as compared with polycrystalline silicon, and which is compatible with conventional MOS LSI fabrication techniques.
A related object of the invention is to provide a low resistivity gate/interconnect structure which is not adversely affected by high temperature deposition processes.
Yet another object of the invention is to provide a low resistivity gate/interconnect structure which can be reliably adhered to a monocrystalline 0 silicon substrate.
Still another object of the invention is to provide a stable gate/interconnect structure which has the conductivity properties of metal and which has the corrosion resistance properties of semi-conductor material.
5 SUMMARY OF THE INVENTION
A further reduction in signal propagation delays and therefore an improvement in device access time for an integrated circuit of the type including MOS field effect transistors implemented on a semiconductor substrate is provided by combining the useful properties of a refractory metal
2„ such as molybdenum with polycrystalline silicon to produce a substantially lower sheet resistance. This improvement is provided by a eomposit conductive gate strip including interleaved layers of polycrystalline silicon and a refractory metal selected from the group consisting of molybdenum, tungsten, platinum and titanium. The polycrystalline silicon and refractory metal are separately
„_ deposited in interleaved layers over the surface of an insulating oxide layer to form a eomposit conductive gate/interconnect layer. The eomposit conductive layer is patterned to produce the gate nodes and interconnection lines such as address and word lines and output buffer gates of the transistors.
The polycrystalline silicon and refractory metal deposits are carried
30 out in separate depositions, thereby yielding interleaved layers of semiconductor and metal.
-, '-.._: . I f According to a preferred embodiment, a layer of molybdenum dsposited on an insulating oxide layer, and a polycrystalline silicon layer deposited onto the molybdenum metal layer. In this arrangement, molybdenu silicide (MoSi is formed at the interface of the layers, which can be easil bonded to the monocrystalline silicon substrate. Additionally, oxidation of th eomposit strip is comparable to that of a single polycrystalline silicon strip, b has a series resistance significantly lower due to the separate molybdenu layer. Even though the molybdenum is relatively resistive as compared wit copper, it substantially reduces the interconnect sheet resistance below that the present state of the art, which is 20 - 30 ohms per square for polycrystalline silicon sheet of 4,000 angstroms thickness.
The eomposit gate structure including the polycrystalline silico layer and the refractory metal layer exhibits the best properties of eac component. Although the polycrystalline silicon has relatively low conductivit (1 x 10 ohm-cm), it is capable of withstanding the MOS processing condition The refractory metal, for example molybdenum, has a relatively hig conductivity (1 x 10 , ohm-cm), but is difficult to process when exposed to th chemical and oxidizing reagents at high temperatures. The eomposit structur on the other hand, has the high melting point, high oxidation resistance an pattern definition capability of polycrystalline silicon alone, and importantl has the substantially lower resistivity of the refractory metal. The eomposi gate/interconnect structure is, therefore, highly compatible with the silico gate processes and is suitable as a gate material for constructing high spee MOS devices.
The novel features which characterize the invention are defined b the appended claims. The foregoing and other objects, advantages and feature of the invention will hereinafter appear, and for purposes of illustration of th invention, but not of limitation, an exemplary embodiment of the invention i shown in the appended drawing.
BRIEF DESCRIPTION OF THE DRAWING
FIGURES 1 - 14 are schematic sectional views illustrating successiv steps of the process of the present invention; FIGURES 15, 16 and 17 are partial substrate views, taken in section, of alternate embodiments of a eomposit gate/interconnect structure.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
In the description which follows, the invention is described in 5 combination with the fabrication of a read only memory (ROM) of the type utilizing insulated gate field ef ect transistor technology.
Like parts are marked throughout the specification and drawings with the same reference numerals, respectively. The drawing figures are not necessarily to scale and in some instances portions have been exaggerated in 0 order to more clearly depict certain features of the invention.
Referring now to the drawings, and in particular to FIGURE 1, a semiconductor substrate 10 is the starting material for the process of the present invention. The semiconductor substrate 10 is typically monocrystalline silicon and may be doped with either N-type or P-type conductivity impurities. g However, the semiconductor substrate 10 may be any conventional type used in the fabrication of insulated gate semiconductor field effect devices; the crystal orientation and doping levels being conventional and well known.
The semiconductor substrate 10 is placed in a conventional oxidizing furnace and a silicon oxide layer 12 is thermally grown to a typical thickness of 0 6,000 angstroms for N-channel deviees or 15,000 angstroms for P-channel devices. Next, a photo-resist layer is applied to the oxide layer 12 and patterned using conventional photo-lithographic techniques to provide an etching mask 14 through which the underlying oxide layer 12 is removed using a conventional selective etching solution at each transistor site, where transistors 5 are to be formed, for example, transistor sites 16a and 16b. The etching mask 14 is then stripped from the oxide layer 12.
The semiconductor substrate 10 is again placed in an oxidizing furnace and a thin gate oxide layer 18 is thermally grown on the surface of the semiconductor substrate 10 to a thickness of from about 600 angstroms to about Q 2,000 angstroms to form the gate insulators for the transistors. This produces a wafer as illustrated in FIGURE 3. Next the oxide wafer 18 is coated with photoresist which is patterned to leave a photoresist mask 20 at each transistor site where no ion implantation is desired, as illustrated in FIGURE 4. If desired, the photoresist mask 20 can be a metallized layer patterned by conventional photolithographic techniques.
Next, the wafer 18 is positioned in ion implantation equipment and the surface of the wafer is subjected to bombardment over its entire surface as represented by the arrows 22 in FIGURE 5. The power of the ions is selected to penetrate the thin gate oxide layer 18 at the site 16a which is not protected by the photoresist mask 20 and lodge in the semiconductor substrate 10 near the surface as represented by the enhanced region 24. However, the ions do not have sufficient velocity to penetrate the photoresist mask 20, or the thick oxide layer 12 which covers the remainder of the slice other than the transistor sites. As a result, the ions are implanted only at those transistor sites which were left unprotected and the operating characteristics of which are to be changed. The level of ion implantation can be selected so as to merely lower the threshold voltage of enhancement mode devices, or can be chosen so as to actually convert the conductivity type of the semiconductor substrate 10 to provide depletion mode devices. The concentration of the ion implantation or dose will hereinafter be discussed in greater detail in connection with FIGURES 14 - 16.
The ions may be derived from boron compounds, such as BF„ to produce P-channei devices, or from phosphorus compounds such as PH . to produce N-channel devices. Equipment for such ion implantation is commercially available, and its use for implantation purposes is well known in the industry.
Next, the photoresist mask 20 is stripped from the semiconductor substrate 10 and a layer of metal having a high melting temperature, for example a refractory metal selected from the group consisting of molybdenum, tungsten, platinum and titanium, is deposited on the surface of the oxide layer 12 and the thin gate oxide layer 18 as illustrated in FIGURE 6. The metal is preferably molybdenum and is deposited in a single film layer, for example 2,000 angstroms thickness, by a molecular beam epitary process, or by planar magnetron sputtering.
Next a layer of polycrystalline silicon 28 is deposited on the surface of the molybdenum layer 26, in a thickness of approximately 2,000 angstroms, with the combined thickness of the interleaved molybdenum/polysilieon layers being in the range of from approximately 3,000 angstroms to 6,000 angstroms. Each deposition is followed by a high temperature step to permit any solid- solubility reaction to go to completion. As a result of this high temperature step, molybdenum-silicide (MoSio) is produced at the interface 30 between the interleaved layers, thereby securely bonding the interleaved layers, both electrically and structurally.
Next, a silicon oxide layer 32 is deposited on the polycrystalline 5 silicon layer 28 using conventional deposition processes.
Then a layer of photoresist is applied to the silicon oxide layer 32 and patterned using conventional photographic techniques to leave photoresist areas 34a and 34b which define the gate geometries of the transistors for the transistor sites 16a and 16b, respectively, as indicated in FIGURE 8. The o semiconductor substrate 10 is then subjected to a selective etch solution which preferentially etches the silicon oxide layer 32, but not the underlying moly/poly layers 26, 28, thus leaving the structure illustrated in FIGURE 9.
Next, the photoresist areas 34a, 34b are stripped and the substrate slice is subjected to an etch solution which preferentially attacks the eomposit 5 molybdenum/polycrystalline silicon layers 26, 28 but not the silicon oxide layer 32. This results in the removal of the polycrystalline silicon layer 26 and the molybdenum layer 28 in all areas except in the eomposit gate areas defined by the interleaved molybdenum and polycrystalline silicon strips, as indicated generally at 36, and which will ultimately be the gate electrode of the 0 transistor. The interleaved gate layers 26, 28 also function as an etching and diffusion mask for the source, drain and interconnect diffusion steps presently to be described.
Next the substrate 10 is subjected to an etching solution which selectively attacks the oxide layer 12 and then gate oxide layer 18, but not the g interleaved molybdenum and polycrystalline silicon layers 26, 28. The duration of this etch is controlled so that only the thin gate oxide layer 18 and the oxide layer 32 of the interleaved gate structure is removed, and the thick oxide layer 12 remains at a substantial thickness as illustrated in FIGURE 11. This results in the semiconductor substrate 10 being exposed only in the areas where diffusion
30 is to be made for source and drain regions, or for lower level interconnects, in which areas the thin oxide layer was also previously formed. Conventional impurity sources for this diffusion step may be used, such as boron compounds, BBr3 and B2Hg for P-ehannel devices and phosphorus compounds for N-channel devices. The diffusion regions which result from this step are indicated at 38 in
35 FIGURE 12.
-g JfEA r Next, an oxide layer 40 is deposited over the surface of the slice a illustrated in FIGURE 13. Openings are then made in the oxide layer 40 usin conventional photolithographic techniques. A metal film is deposited over th oxide layer 40 in the openings, and is patterned to produce the structur illustrated in FIGURE 14 having source and drain contacts 42, 44, respectively and gate contacts 46 for the transistors at sites 16a and 16b. The devic illustrated in FIGURE 14 may include a final silicon dioxide passivating laye (not illustrated) deposited over the entire structure, except for over bondin pads at the periphery of the chip.
The self-aligned gate structure provided by using the interleave molybdenum/polycrystalline silicon gate strips as the etching mask for removin the oxide layer reduces capacitance and thus significantly increases the spee of operation of the circuit. The interleaved molybdenum/polycrystalline silico layers 26, 28 can also be used as a eomposit interconnecting conductor 36, an thus can provide a third layer of interconnection to increase the functiona density of the integrated circuit. Various alternative combinations of th molybdenum layer 26 with the polycrystalline silicon layer 28 are illustrated i FIGURES 15, 16 and 17, as used for interconnect lines over the oxide layer 12 The interconnect structure shown in FIGURE 15 is produced by first depositing film layer of molybdenum over the oxide layer 12, then followed by th deposition of a film of polycrystalline silicon 28 over the molybdenum layer.
The interconnect structure shown in FIGURE 16 is produced b similar steps, except that the first layer is formed by depositing a film o polycrystalline silicon 28 over the oxide layer 12, followed by the deposition of molybdenum layer 26, with a final layer of polycrystalline silicon deposited ove the molybdenum layer 26. This structure is extremely stable and is highl compatible with MOS processing conditions. In the structure of either FIGUR 15 or 16, the molybdenum metal layer is protected by the polycrystalline silico layer 28, which serves as a shield against the reagents of the MOS processin steps, and can be easily oxidized.
An alternative embodiment is illustrated in FIGURE 17 in which th polycrystalline silicon layer 28 is deposited first, followed by the deposition of molybdenum film layer 26. This arrangement has the advantage of being easil bonded to the polysilicon layer, and has the relatively lower sheet resistivity, but cannot withstand severe exposure to chemical reagents at hig temperatures. The eomposit gate/interconnect structures illustrated in FIGURES 15 and 16 are oxidizable in the same manner as a single strip of polycrystalline silicon, but have a sheet resistance significantly lower due to the molybdenum layer 26. Even though molybdenum is relatively more resistive than copper or silver, it significantly reduces the gate/interconnect resistance to 4 - 10 ohms per square, well below that of the present state of the art, which is in the range of 20 - 30 ohms per square for a sheet of polycrystalline silicon having a thickness of 4,000 angstroms. The combination of the polycrystalline silicon layer with a layer of a refractory metal such as molybdenum exhibits the advantages of conventional polycrystalline silicon gate/interconnect structures in terms of processing, and provides the added advantage of lower sheet resistance, without the corrosion problems encountered with using only molybdenum by itself.
With the lower sheet resistance of the eomposit gate/interconnect structure, signal propagation delays are reduced, thereby allowing devices such as read only memories to achieve higher operating speeds as the packing density increases and as the geometry is scaled down.
Although preferred embodiments of the invention have been described in detail, it is to be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions of parts and elements without departing from the spirit of the invention.

Claims

Claims *• In an integrated circuit of the type implemented on a semiconductor substrate in which active components of one conductivity type are disposed on a substrate field of the opposite conductivity type, an improved conductor electrically interconnecting said active components comprising interleaved layers of polycrystalline silicon and metal.
5
2. The integrated circuit as defined in Claim 1, said metal comprising molybdenum.
3. In an integrated circuit of the type including a substrate of 0 semiconductor material, said substrate including an active surface area surrounded by a substrate field area defining the situs of a transistor having source and drain regions, and a strip of gate insulating material overlying the active situs area, the improvement comprising a composite conductive gate strip deposited on said gate insulating strip, said composite conductive gate _ strip including interleaved layers of polycrystalline silicon and a refractory metal selected from the group consisting of molybdenum, tungsten, platinum and titanium.
4. The integrated circuit as defined in Claim 3, said refractory metal layer being deposited on said gate insulating strip, and said 0 polycrystalline silicon layer being deposited on said refractory metal layer.
5. The integrated circuit as defined in Claim 3, said polycrystalline silicon layer being deposited on said gate insulating strip, and said refractory metal layer being deposited on said polycrystalline silicon layer. 5
6. The integrated circuit as defined in Claim 5, including a second polycrystalline silicon layer deposited on said refractory metal layer.
7. The integrated circuit as defined in Claim 3, said eomposit conductive gate strip comprising polycrystalline silicon and said refractory 0 metal comprising molybdenum.
8. In an integrated circuit memory of the type including an array of memory cells fabricated on a semiconductor substrate in rows and columns, each cell including principal components interconnected to store bits of binary data, an improved interconnect structure comprising a layer of electrical insulating material deposited on said substrate, and a eomposit conductive layer deposited on said insulating layer and electrically coupled to one of said cells, said eomposit conductive layer including interleaved layers of polycrystalline silicon and a metal having a relatively high melting temperature.
9. The integrated circuit memory as defined in Claim 8, said metal being a refractory metal selected from the group consisting of molybdenum, tungsten, platinum and titanium.
10. A method for producing an integrated circuit having a plurality of field effect transistors comprising: forming an oxide layer on the surface of semiconductor substrate having relatively thin oxide areas defining a plurality of transistor sites each including source, drain and channel regions, and also diffused interconnect paths, and thick oxide areas over substantially the remainder of the portion of the substrate forming the integrated circuit; depositing interleaved layers of polycrystalline silicon and metal over the surface of the oxide layer to form a eomposit conductive layer; patterning the eomposit conductive layer to form the gate nodes of the respective transistors, the gate nodes overlying the areas of the oxide layer that are relatively thin and delineating the areas of the channels of the respective transistors; removing the relatively thin areas of the oxide layer which are not covered by the eomposit conductive layer but not the relatively thick oxide areas to leave the substrate exposed in areas defining the source and drain regions of the transistors and the diffused interconnect paths of the integrated circuit; diffusing impurities through the exposed areas of the surface of the substrate until the regions of the substrate underlying the exposed surface areas are converted to the opposite conductivity-type; depositing a second oxide layer over the substrate structure and removing portions of the second oxide layer to leave selected gate, source and drain nodes exposed; and, forming a plurality of conductive interconnects between the exposed nodes to produce an integrated circuit.
11. The method as defined in- Claim 10, wherein the step of depositing said eomposit conductive layer is performed by first depositing a layer of metal on said oxide layer and thereafter depositing a layer of polycrystalline silicon on said metal layer.
12. The method as defined in Claim 10, wherein the step of depositing said eomposit conductive layer is performed by first depositing a layer of polycrystalline silicon on said oxide layer and thereafter depositing a layer of metal on said polycrystalline silicon layer.
13. The method as defined in Claim 12, including the step of depositing an additional layer of polycrystalline silicon on said metal layer.
C-. .
PCT/US1980/000652 1980-01-21 1980-05-22 Composit gate interconnect structure WO1981002222A1 (en)

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Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0087573A2 (en) * 1982-02-26 1983-09-07 International Business Machines Corporation Method of making complementary field effect transistors
EP0115287A2 (en) * 1983-01-27 1984-08-08 Kabushiki Kaisha Toshiba Semiconductor device including a metal silicide
EP0163132A1 (en) * 1984-04-27 1985-12-04 Kabushiki Kaisha Toshiba A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of CMOS inverters
EP0207486A1 (en) * 1985-07-02 1987-01-07 Siemens Aktiengesellschaft Integrated circuit containing MOS transistors and comprising a gate metallization of a metal or a metal silicide of the elements tantalum or niobium, as well as a method of producing this gate metallization
US4941034A (en) * 1985-10-22 1990-07-10 Siemens Aktiengesellschaft Integrated semiconductor circuit
WO1994014198A1 (en) * 1992-12-11 1994-06-23 Intel Corporation A mos transistor having a composite gate electrode and method of fabrication
US6255705B1 (en) * 1997-09-23 2001-07-03 Semiconductor Energy Laboratory Co., Ltd. Producing devices having both active matrix display circuits and peripheral circuits on a same substrate

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3189973A (en) * 1961-11-27 1965-06-22 Bell Telephone Labor Inc Method of fabricating a semiconductor device
US3402081A (en) * 1965-06-30 1968-09-17 Ibm Method for controlling the electrical characteristics of a semiconductor surface and product produced thereby
US3519901A (en) * 1968-01-29 1970-07-07 Texas Instruments Inc Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation
US3881242A (en) * 1972-11-08 1975-05-06 Ferranti Ltd Methods of manufacturing semiconductor devices
US3936865A (en) * 1973-02-28 1976-02-03 U.S. Philips Corporation Semiconductor devices having conductor tracks at different levels and interconnections therebetween
US4029562A (en) * 1976-04-29 1977-06-14 Ibm Corporation Forming feedthrough connections for multi-level interconnections metallurgy systems
US4042953A (en) * 1973-08-01 1977-08-16 Micro Power Systems, Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4096510A (en) * 1974-08-19 1978-06-20 Matsushita Electric Industrial Co., Ltd. Thermal printing head
US4146902A (en) * 1975-12-03 1979-03-27 Nippon Telegraph And Telephone Public Corp. Irreversible semiconductor switching element and semiconductor memory device utilizing the same
US4219379A (en) * 1978-09-25 1980-08-26 Mostek Corporation Method for making a semiconductor device
US4222062A (en) * 1976-05-04 1980-09-09 American Microsystems, Inc. VMOS Floating gate memory device

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3189973A (en) * 1961-11-27 1965-06-22 Bell Telephone Labor Inc Method of fabricating a semiconductor device
US3402081A (en) * 1965-06-30 1968-09-17 Ibm Method for controlling the electrical characteristics of a semiconductor surface and product produced thereby
US3519901A (en) * 1968-01-29 1970-07-07 Texas Instruments Inc Bi-layer insulation structure including polycrystalline semiconductor material for integrated circuit isolation
US3881242A (en) * 1972-11-08 1975-05-06 Ferranti Ltd Methods of manufacturing semiconductor devices
US3936865A (en) * 1973-02-28 1976-02-03 U.S. Philips Corporation Semiconductor devices having conductor tracks at different levels and interconnections therebetween
US4042953A (en) * 1973-08-01 1977-08-16 Micro Power Systems, Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4096510A (en) * 1974-08-19 1978-06-20 Matsushita Electric Industrial Co., Ltd. Thermal printing head
US4146902A (en) * 1975-12-03 1979-03-27 Nippon Telegraph And Telephone Public Corp. Irreversible semiconductor switching element and semiconductor memory device utilizing the same
US4029562A (en) * 1976-04-29 1977-06-14 Ibm Corporation Forming feedthrough connections for multi-level interconnections metallurgy systems
US4222062A (en) * 1976-05-04 1980-09-09 American Microsystems, Inc. VMOS Floating gate memory device
US4219379A (en) * 1978-09-25 1980-08-26 Mostek Corporation Method for making a semiconductor device

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0087573A2 (en) * 1982-02-26 1983-09-07 International Business Machines Corporation Method of making complementary field effect transistors
EP0087573A3 (en) * 1982-02-26 1986-09-17 International Business Machines Corporation Method of making complementary field effect transistors
EP0115287A2 (en) * 1983-01-27 1984-08-08 Kabushiki Kaisha Toshiba Semiconductor device including a metal silicide
EP0115287A3 (en) * 1983-01-27 1987-04-08 Kabushiki Kaisha Toshiba Semiconductor device including a metal silicide
EP0163132A1 (en) * 1984-04-27 1985-12-04 Kabushiki Kaisha Toshiba A semiconductor memory device comprising a matrix of six-transistor memory cells with a pair of CMOS inverters
EP0207486A1 (en) * 1985-07-02 1987-01-07 Siemens Aktiengesellschaft Integrated circuit containing MOS transistors and comprising a gate metallization of a metal or a metal silicide of the elements tantalum or niobium, as well as a method of producing this gate metallization
US4941034A (en) * 1985-10-22 1990-07-10 Siemens Aktiengesellschaft Integrated semiconductor circuit
WO1994014198A1 (en) * 1992-12-11 1994-06-23 Intel Corporation A mos transistor having a composite gate electrode and method of fabrication
GB2286723A (en) * 1992-12-11 1995-08-23 Intel Corp A mos transistor having a composite gate electrode and method of fabrication
GB2286723B (en) * 1992-12-11 1997-01-08 Intel Corp A mos transistor having a composite gate electrode and method of fabrication
US5625217A (en) * 1992-12-11 1997-04-29 Intel Corporation MOS transistor having a composite gate electrode and method of fabrication
US5783478A (en) * 1992-12-11 1998-07-21 Intel Corporation Method of frabricating a MOS transistor having a composite gate electrode
KR100327875B1 (en) * 1992-12-11 2002-09-05 인텔 코오퍼레이션 MOS transistor with composite gate electrode and manufacturing method
US6255705B1 (en) * 1997-09-23 2001-07-03 Semiconductor Energy Laboratory Co., Ltd. Producing devices having both active matrix display circuits and peripheral circuits on a same substrate

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