IT7821202A0 - Circuito di accesso di lettura e/o registrazione per memorie. - Google Patents

Circuito di accesso di lettura e/o registrazione per memorie.

Info

Publication number
IT7821202A0
IT7821202A0 IT7821202A IT2120278A IT7821202A0 IT 7821202 A0 IT7821202 A0 IT 7821202A0 IT 7821202 A IT7821202 A IT 7821202A IT 2120278 A IT2120278 A IT 2120278A IT 7821202 A0 IT7821202 A0 IT 7821202A0
Authority
IT
Italy
Prior art keywords
reading
memory
access circuit
recording access
recording
Prior art date
Application number
IT7821202A
Other languages
English (en)
Other versions
IT1110464B (it
Original Assignee
Armonk New York U S A Internat
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Armonk New York U S A Internat filed Critical Armonk New York U S A Internat
Publication of IT7821202A0 publication Critical patent/IT7821202A0/it
Application granted granted Critical
Publication of IT1110464B publication Critical patent/IT1110464B/it

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Databases & Information Systems (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)
IT21202/78A 1977-03-23 1978-03-15 Circuito di accesso di lettura e/o registrazione per memorie IT1110464B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2712735A DE2712735B1 (de) 1977-03-23 1977-03-23 Lese-/Schreibzugriffschaltung zu Speicherzellen eines Speichers und Verfahren zu ihrem Betrieb

Publications (2)

Publication Number Publication Date
IT7821202A0 true IT7821202A0 (it) 1978-03-15
IT1110464B IT1110464B (it) 1985-12-23

Family

ID=6004436

Family Applications (1)

Application Number Title Priority Date Filing Date
IT21202/78A IT1110464B (it) 1977-03-23 1978-03-15 Circuito di accesso di lettura e/o registrazione per memorie

Country Status (8)

Country Link
US (1) US4112512A (it)
JP (1) JPS6044751B2 (it)
DE (1) DE2712735B1 (it)
FR (1) FR2385179A1 (it)
GB (1) GB1560367A (it)
IT (1) IT1110464B (it)
NL (1) NL7803023A (it)
SE (1) SE422853B (it)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2855118C2 (de) * 1978-12-20 1981-03-26 IBM Deutschland GmbH, 70569 Stuttgart Dynamischer FET-Speicher
US4274013A (en) * 1979-02-09 1981-06-16 Bell Telephone Laboratories, Incorporated Sense amplifier
JPS595989B2 (ja) * 1980-02-16 1984-02-08 富士通株式会社 スタティック型ランダムアクセスメモリ
US4344156A (en) * 1980-10-10 1982-08-10 Inmos Corporation High speed data transfer for a semiconductor memory
JPS589285A (ja) * 1981-07-08 1983-01-19 Toshiba Corp 半導体装置
DE3173745D1 (en) * 1981-10-30 1986-03-20 Ibm Deutschland Fet memory
JPS6151692A (ja) * 1984-08-22 1986-03-14 Hitachi Ltd 記憶装置
JPS61239493A (ja) * 1985-04-05 1986-10-24 Fujitsu Ltd 半導体記憶装置
JPH0766664B2 (ja) * 1988-11-28 1995-07-19 日本電気株式会社 半導体メモリ回路
JPH0762955B2 (ja) * 1989-05-15 1995-07-05 株式会社東芝 ダイナミック型ランダムアクセスメモリ
JPH02301097A (ja) * 1989-05-15 1990-12-13 Toshiba Corp ダイナミック型ランダムアクセスメモリ
JPH03154288A (ja) * 1989-11-10 1991-07-02 Mitsubishi Electric Corp 半導体記憶装置
JP2781080B2 (ja) * 1991-04-09 1998-07-30 三菱電機株式会社 ランダムアクセスメモリ
US5907251A (en) * 1996-11-22 1999-05-25 International Business Machines Corp. Low voltage swing capacitive bus driver device
US6195027B1 (en) 1999-04-30 2001-02-27 International Business Machines Corporation Capacitive precharging and discharging network for converting N bit input into M bit output
US6549476B2 (en) * 2001-04-09 2003-04-15 Micron Technology, Inc. Device and method for using complementary bits in a memory array
US6791859B2 (en) * 2001-11-20 2004-09-14 Micron Technology, Inc. Complementary bit PCRAM sense amplifier and method of operation
US6791885B2 (en) 2002-02-19 2004-09-14 Micron Technology, Inc. Programmable conductor random access memory and method for sensing same
US6731528B2 (en) * 2002-05-03 2004-05-04 Micron Technology, Inc. Dual write cycle programmable conductor memory system and method of operation
JP2012114215A (ja) * 2010-11-24 2012-06-14 Elpida Memory Inc 半導体装置及びそのレイアウト方法
WO2013158088A1 (en) * 2012-04-18 2013-10-24 Hewlett-Packard Development Company, L.P. Circuit providing dc voltages to differential signal lines via restore pulse

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3676704A (en) * 1970-12-29 1972-07-11 Ibm Monolithic memory sense amplifier/bit driver
US3760381A (en) * 1972-06-30 1973-09-18 Ibm Stored charge memory detection circuit
US3771147A (en) * 1972-12-04 1973-11-06 Bell Telephone Labor Inc Igfet memory system
US3806898A (en) * 1973-06-29 1974-04-23 Ibm Regeneration of dynamic monolithic memories
US3949381A (en) * 1974-07-23 1976-04-06 International Business Machines Corporation Differential charge transfer sense amplifier
US3967252A (en) * 1974-10-03 1976-06-29 Mostek Corporation Sense AMP for random access memory

Also Published As

Publication number Publication date
SE422853B (sv) 1982-03-29
DE2712735B1 (de) 1978-09-14
FR2385179A1 (fr) 1978-10-20
IT1110464B (it) 1985-12-23
JPS53117344A (en) 1978-10-13
DE2712735C2 (it) 1979-05-17
GB1560367A (en) 1980-02-06
FR2385179B1 (it) 1980-01-04
US4112512A (en) 1978-09-05
NL7803023A (nl) 1978-09-26
SE7803096L (sv) 1978-09-24
JPS6044751B2 (ja) 1985-10-05

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