SE7812716L - Databuffertminne - Google Patents
DatabuffertminneInfo
- Publication number
- SE7812716L SE7812716L SE7812716D SE7812716D SE7812716L SE 7812716 L SE7812716 L SE 7812716L SE 7812716 D SE7812716 D SE 7812716D SE 7812716 D SE7812716 D SE 7812716D SE 7812716 L SE7812716 L SE 7812716L
- Authority
- SE
- Sweden
- Prior art keywords
- buffer memory
- data buffer
- data
- memory
- buffer
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7713707A NL7713707A (nl) | 1977-12-12 | 1977-12-12 | Informatiebuffergeheugen van het "eerst-in, eerst-uit" type met variabele ingang en vaste uitgang. |
Publications (1)
Publication Number | Publication Date |
---|---|
SE7812716L true SE7812716L (sv) | 1979-06-13 |
Family
ID=19829732
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE7812716A SE437581B (sv) | 1977-12-12 | 1978-12-11 | Databuffertminne |
SE7812716D SE7812716L (sv) | 1977-12-12 | 1978-12-11 | Databuffertminne |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SE7812716A SE437581B (sv) | 1977-12-12 | 1978-12-11 | Databuffertminne |
Country Status (9)
Country | Link |
---|---|
US (1) | US4236225A (sv) |
JP (1) | JPS5920139B2 (sv) |
CA (1) | CA1122329A (sv) |
DE (1) | DE2853239A1 (sv) |
FR (1) | FR2411467A1 (sv) |
GB (1) | GB2009984B (sv) |
IT (1) | IT1101479B (sv) |
NL (1) | NL7713707A (sv) |
SE (2) | SE437581B (sv) |
Families Citing this family (29)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57164331A (en) * | 1981-04-02 | 1982-10-08 | Nec Corp | Buffer controller |
JPS57185492A (en) * | 1981-05-11 | 1982-11-15 | Matsushita Electric Ind Co Ltd | Data latch circuit |
JPS58220293A (ja) * | 1982-06-15 | 1983-12-21 | Nec Corp | 記憶装置 |
US4510581A (en) * | 1983-02-14 | 1985-04-09 | Prime Computer, Inc. | High speed buffer allocation apparatus |
US4930102A (en) * | 1983-04-29 | 1990-05-29 | The Regents Of The University Of California | Dynamic activity-creating data-driven computer architecture |
JPS59226923A (ja) * | 1983-05-27 | 1984-12-20 | インタ−ナシヨナル ビジネス マシ−ンズ コ−ポレ−シヨン | バスインタ−フエ−ス装置 |
US4598363A (en) * | 1983-07-07 | 1986-07-01 | At&T Bell Laboratories | Adaptive delayed polling of sensors |
US4592019A (en) * | 1983-08-31 | 1986-05-27 | At&T Bell Laboratories | Bus oriented LIFO/FIFO memory |
FR2552916B1 (fr) * | 1983-09-29 | 1988-06-10 | Thomas Alain | File d'attente asynchrone a empilement de registres |
US5038277A (en) * | 1983-11-07 | 1991-08-06 | Digital Equipment Corporation | Adjustable buffer for data communications in a data processing system |
AU575351B2 (en) * | 1983-11-07 | 1988-07-28 | Digital Equipment Corporation | Data processing system |
US4764894A (en) * | 1985-01-16 | 1988-08-16 | Varian Associates, Inc. | Multiple FIFO NMR acquisition system |
US4833655A (en) * | 1985-06-28 | 1989-05-23 | Wang Laboratories, Inc. | FIFO memory with decreased fall-through delay |
NL8502023A (nl) * | 1985-07-15 | 1987-02-02 | Philips Nv | Werkwijze voor het schakelen van tijdsloten in een tdm-signaal en inrichting voor het uitvoeren van de werkwijze. |
US4672646A (en) * | 1986-09-16 | 1987-06-09 | Hewlett-Packard Company | Direct-injection FIFO shift register |
US4847812A (en) * | 1986-09-18 | 1989-07-11 | Advanced Micro Devices | FIFO memory device including circuit for generating flag signals |
US4995005A (en) * | 1986-09-18 | 1991-02-19 | Advanced Micro Devices, Inc. | Memory device which can function as two separate memories or a single memory |
JPS648732A (en) * | 1987-06-30 | 1989-01-12 | Sharp Kk | Digital serial/parallel converter |
US5115496A (en) * | 1988-01-26 | 1992-05-19 | Nec Corporation | Queue device capable of quickly transferring a digital signal unit of a word length different from a single word length |
JP2764908B2 (ja) * | 1988-02-04 | 1998-06-11 | 日本電気株式会社 | カスケード・バッファ回路 |
JP2576616B2 (ja) * | 1988-12-29 | 1997-01-29 | カシオ計算機株式会社 | 処理装置 |
JPH0391188A (ja) * | 1989-09-04 | 1991-04-16 | Matsushita Electric Ind Co Ltd | Fifoメモリ |
US5095462A (en) * | 1990-05-25 | 1992-03-10 | Advanced Micro Devices, Inc. | Fifo information storage apparatus including status and logic modules for each cell |
US5412611A (en) * | 1992-03-17 | 1995-05-02 | Fujitsu, Limited | FIFO memory device capable of writing contiguous data into rows |
US5513224A (en) * | 1993-09-16 | 1996-04-30 | Codex, Corp. | Fill level indicator for self-timed fifo |
JP3736855B2 (ja) * | 1995-07-10 | 2006-01-18 | ジーリンクス インコーポレイテッド | フィールドプログラマブル・ゲートアレイ及びインテリジェント・メモリを含んでいるシステム |
KR100594953B1 (ko) | 1997-08-20 | 2006-07-03 | 코닌클리케 필립스 일렉트로닉스 엔.브이. | 다중레벨의 하우스키핑을 위해 적합한 소프트웨어 관리 기능을 갖는 임시 데이터스트림 신호처리 버퍼 메모리 구조 |
JP4841314B2 (ja) * | 2006-05-29 | 2011-12-21 | 川崎マイクロエレクトロニクス株式会社 | データ転送回路 |
JP6568560B2 (ja) | 2017-09-15 | 2019-08-28 | 株式会社Subaru | 車両の走行制御装置 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL6600550A (sv) * | 1966-01-15 | 1967-07-17 | ||
US3646526A (en) * | 1970-03-17 | 1972-02-29 | Us Army | Fifo shift register memory with marker and data bit storage |
NL7014737A (sv) * | 1970-10-08 | 1972-04-11 | ||
GB1289249A (sv) * | 1971-05-05 | 1972-09-13 | ||
US3781821A (en) * | 1972-06-02 | 1973-12-25 | Ibm | Selective shift register |
US3942163A (en) * | 1974-06-21 | 1976-03-02 | Burroughs Corporation | CCD stack memory organization |
US3953838A (en) * | 1974-12-30 | 1976-04-27 | Burroughs Corporation | FIFO Buffer register memory utilizing a one-shot data transfer system |
JPS5247638A (en) * | 1975-10-15 | 1977-04-15 | Toshiba Corp | Information processing device |
US4095283A (en) * | 1976-07-02 | 1978-06-13 | International Business Machines Corporation | First in-first out memory array containing special bits for replacement addressing |
-
1977
- 1977-12-12 NL NL7713707A patent/NL7713707A/xx not_active Application Discontinuation
-
1978
- 1978-11-30 US US05/965,208 patent/US4236225A/en not_active Expired - Lifetime
- 1978-12-07 IT IT30681/78A patent/IT1101479B/it active
- 1978-12-07 CA CA317,576A patent/CA1122329A/en not_active Expired
- 1978-12-08 GB GB7847707A patent/GB2009984B/en not_active Expired
- 1978-12-09 JP JP53152598A patent/JPS5920139B2/ja not_active Expired
- 1978-12-09 DE DE19782853239 patent/DE2853239A1/de active Granted
- 1978-12-11 FR FR7834812A patent/FR2411467A1/fr active Granted
- 1978-12-11 SE SE7812716A patent/SE437581B/sv not_active IP Right Cessation
- 1978-12-11 SE SE7812716D patent/SE7812716L/sv not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
IT1101479B (it) | 1985-09-28 |
US4236225A (en) | 1980-11-25 |
DE2853239C2 (sv) | 1989-02-02 |
GB2009984A (en) | 1979-06-20 |
CA1122329A (en) | 1982-04-20 |
GB2009984B (en) | 1982-01-27 |
SE437581B (sv) | 1985-03-04 |
DE2853239A1 (de) | 1979-06-13 |
JPS5489439A (en) | 1979-07-16 |
NL7713707A (nl) | 1979-06-14 |
JPS5920139B2 (ja) | 1984-05-11 |
FR2411467A1 (fr) | 1979-07-06 |
FR2411467B1 (sv) | 1985-01-18 |
IT7830681A0 (it) | 1978-12-07 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
NAV | Patent application has lapsed |
Ref document number: 7713707-3 |