FR2446011A1 - Dispositif mos a contacts autoalignes et son procede de fabrication - Google Patents

Dispositif mos a contacts autoalignes et son procede de fabrication

Info

Publication number
FR2446011A1
FR2446011A1 FR8000237A FR8000237A FR2446011A1 FR 2446011 A1 FR2446011 A1 FR 2446011A1 FR 8000237 A FR8000237 A FR 8000237A FR 8000237 A FR8000237 A FR 8000237A FR 2446011 A1 FR2446011 A1 FR 2446011A1
Authority
FR
France
Prior art keywords
self
manufacturing
mos device
aligned contact
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8000237A
Other languages
English (en)
French (fr)
Other versions
FR2446011B3 (enExample
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
American Microsystems Holding Corp
Original Assignee
American Microsystems Holding Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Microsystems Holding Corp filed Critical American Microsystems Holding Corp
Publication of FR2446011A1 publication Critical patent/FR2446011A1/fr
Application granted granted Critical
Publication of FR2446011B3 publication Critical patent/FR2446011B3/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
FR8000237A 1979-01-08 1980-01-07 Dispositif mos a contacts autoalignes et son procede de fabrication Granted FR2446011A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US184079A 1979-01-08 1979-01-08

Publications (2)

Publication Number Publication Date
FR2446011A1 true FR2446011A1 (fr) 1980-08-01
FR2446011B3 FR2446011B3 (enExample) 1981-11-06

Family

ID=21698078

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8000237A Granted FR2446011A1 (fr) 1979-01-08 1980-01-07 Dispositif mos a contacts autoalignes et son procede de fabrication

Country Status (7)

Country Link
JP (1) JPS5593271A (enExample)
CA (1) CA1131796A (enExample)
DE (1) DE3000121A1 (enExample)
FR (1) FR2446011A1 (enExample)
GB (1) GB2040564A (enExample)
IT (1) IT8019078A0 (enExample)
NL (1) NL7908534A (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455737A (en) * 1978-05-26 1984-06-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4409722A (en) * 1980-08-29 1983-10-18 International Business Machines Corporation Borderless diffusion contact process and structure
US4341009A (en) * 1980-12-05 1982-07-27 International Business Machines Corporation Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate
JPS57113289A (en) * 1980-12-30 1982-07-14 Fujitsu Ltd Semiconductor device and its manufacture
US4517729A (en) * 1981-07-27 1985-05-21 American Microsystems, Incorporated Method for fabricating MOS device with self-aligned contacts
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
JPS63207171A (ja) * 1987-02-24 1988-08-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ装置及びその製造方法
US5159353A (en) * 1991-07-02 1992-10-27 Hewlett-Packard Company Thermal inkjet printhead structure and method for making the same
KR100377833B1 (ko) * 2001-06-19 2003-03-29 삼성전자주식회사 보더리스 콘택 구조를 갖는 반도체 장치 및 그 제조방법

Also Published As

Publication number Publication date
CA1131796A (en) 1982-09-14
DE3000121A1 (de) 1980-07-17
GB2040564A (en) 1980-08-28
NL7908534A (nl) 1980-07-10
IT8019078A0 (it) 1980-01-08
FR2446011B3 (enExample) 1981-11-06
JPS5593271A (en) 1980-07-15

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