FR2446011A1 - Dispositif mos a contacts autoalignes et son procede de fabrication - Google Patents
Dispositif mos a contacts autoalignes et son procede de fabricationInfo
- Publication number
- FR2446011A1 FR2446011A1 FR8000237A FR8000237A FR2446011A1 FR 2446011 A1 FR2446011 A1 FR 2446011A1 FR 8000237 A FR8000237 A FR 8000237A FR 8000237 A FR8000237 A FR 8000237A FR 2446011 A1 FR2446011 A1 FR 2446011A1
- Authority
- FR
- France
- Prior art keywords
- self
- manufacturing
- mos device
- aligned contact
- source
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Ce procédé réduit la surface de pastille d'un transistor MOS 10a. Les contacts de la source 12a, du drain 14a et de la grille 16a, qui ont tous une surface minimale, sont alignés automatiquement avec les bords de la région source-drain 18a ou de l'électrode de grille 20a et avec l'oxyde de champ à l'entour. Les tolérances L1 , L2 et L 3 sont réduites à zéro et chaque région diffusée 18a peut présenter des dimensions minimales en longueur et en largeur. Applications notamment aux dispositifs semi-conducteurs à circuits intégrés.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US184079A | 1979-01-08 | 1979-01-08 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2446011A1 true FR2446011A1 (fr) | 1980-08-01 |
FR2446011B3 FR2446011B3 (fr) | 1981-11-06 |
Family
ID=21698078
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR8000237A Granted FR2446011A1 (fr) | 1979-01-08 | 1980-01-07 | Dispositif mos a contacts autoalignes et son procede de fabrication |
Country Status (7)
Country | Link |
---|---|
JP (1) | JPS5593271A (fr) |
CA (1) | CA1131796A (fr) |
DE (1) | DE3000121A1 (fr) |
FR (1) | FR2446011A1 (fr) |
GB (1) | GB2040564A (fr) |
IT (1) | IT8019078A0 (fr) |
NL (1) | NL7908534A (fr) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4455737A (en) * | 1978-05-26 | 1984-06-26 | Rockwell International Corporation | Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines |
US4506437A (en) * | 1978-05-26 | 1985-03-26 | Rockwell International Corporation | Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines |
US4409722A (en) * | 1980-08-29 | 1983-10-18 | International Business Machines Corporation | Borderless diffusion contact process and structure |
US4341009A (en) * | 1980-12-05 | 1982-07-27 | International Business Machines Corporation | Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate |
JPS57113289A (en) * | 1980-12-30 | 1982-07-14 | Fujitsu Ltd | Semiconductor device and its manufacture |
US4517729A (en) * | 1981-07-27 | 1985-05-21 | American Microsystems, Incorporated | Method for fabricating MOS device with self-aligned contacts |
US4686000A (en) * | 1985-04-02 | 1987-08-11 | Heath Barbara A | Self-aligned contact process |
JPS63207171A (ja) * | 1987-02-24 | 1988-08-26 | Nippon Telegr & Teleph Corp <Ntt> | 半導体メモリ装置及びその製造方法 |
US5159353A (en) * | 1991-07-02 | 1992-10-27 | Hewlett-Packard Company | Thermal inkjet printhead structure and method for making the same |
KR100377833B1 (ko) * | 2001-06-19 | 2003-03-29 | 삼성전자주식회사 | 보더리스 콘택 구조를 갖는 반도체 장치 및 그 제조방법 |
-
1979
- 1979-11-14 CA CA339,798A patent/CA1131796A/fr not_active Expired
- 1979-11-21 GB GB7940199A patent/GB2040564A/en not_active Withdrawn
- 1979-11-23 NL NL7908534A patent/NL7908534A/nl not_active Application Discontinuation
-
1980
- 1980-01-03 DE DE19803000121 patent/DE3000121A1/de not_active Withdrawn
- 1980-01-07 FR FR8000237A patent/FR2446011A1/fr active Granted
- 1980-01-08 IT IT8019078A patent/IT8019078A0/it unknown
- 1980-01-08 JP JP83180A patent/JPS5593271A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
IT8019078A0 (it) | 1980-01-08 |
CA1131796A (fr) | 1982-09-14 |
FR2446011B3 (fr) | 1981-11-06 |
DE3000121A1 (de) | 1980-07-17 |
NL7908534A (nl) | 1980-07-10 |
JPS5593271A (en) | 1980-07-15 |
GB2040564A (en) | 1980-08-28 |
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