GB2040564A - Method of fabricating MOSFETs - Google Patents

Method of fabricating MOSFETs Download PDF

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Publication number
GB2040564A
GB2040564A GB7940199A GB7940199A GB2040564A GB 2040564 A GB2040564 A GB 2040564A GB 7940199 A GB7940199 A GB 7940199A GB 7940199 A GB7940199 A GB 7940199A GB 2040564 A GB2040564 A GB 2040564A
Authority
GB
United Kingdom
Prior art keywords
layer
source
drain regions
gate
gate electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
GB7940199A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
American Microsystems Holding Corp
Original Assignee
American Microsystems Holding Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Microsystems Holding Corp filed Critical American Microsystems Holding Corp
Publication of GB2040564A publication Critical patent/GB2040564A/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
GB7940199A 1979-01-08 1979-11-21 Method of fabricating MOSFETs Withdrawn GB2040564A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US184079A 1979-01-08 1979-01-08

Publications (1)

Publication Number Publication Date
GB2040564A true GB2040564A (en) 1980-08-28

Family

ID=21698078

Family Applications (1)

Application Number Title Priority Date Filing Date
GB7940199A Withdrawn GB2040564A (en) 1979-01-08 1979-11-21 Method of fabricating MOSFETs

Country Status (7)

Country Link
JP (1) JPS5593271A (enExample)
CA (1) CA1131796A (enExample)
DE (1) DE3000121A1 (enExample)
FR (1) FR2446011A1 (enExample)
GB (1) GB2040564A (enExample)
IT (1) IT8019078A0 (enExample)
NL (1) NL7908534A (enExample)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0055932A1 (en) * 1980-12-30 1982-07-14 Fujitsu Limited Schottky gate electrode for a compound semiconductor device, and method of manufacturing it
EP0054163A3 (en) * 1980-12-05 1983-08-03 International Business Machines Corporation Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate and method for making a field effect transistor
FR2533370A1 (fr) * 1982-09-22 1984-03-23 American Micro Syst Procede de fabrication d'un dispositif mos a contacts auto-alignes
US4455737A (en) * 1978-05-26 1984-06-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
EP0200372A3 (en) * 1985-04-02 1988-04-27 Inmos Corporation Self-aligned contact window formation in an integrated circuit
EP0521634A3 (en) * 1991-07-02 1993-05-12 Hewlett-Packard Company Improved thermal inkjet printhead structure and method for making the same
GB2381657A (en) * 2001-06-19 2003-05-07 Samsung Electronics Co Ltd Borderless contact structure

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4409722A (en) * 1980-08-29 1983-10-18 International Business Machines Corporation Borderless diffusion contact process and structure
JPS63207171A (ja) * 1987-02-24 1988-08-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ装置及びその製造方法

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4455737A (en) * 1978-05-26 1984-06-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
EP0054163A3 (en) * 1980-12-05 1983-08-03 International Business Machines Corporation Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate and method for making a field effect transistor
EP0055932A1 (en) * 1980-12-30 1982-07-14 Fujitsu Limited Schottky gate electrode for a compound semiconductor device, and method of manufacturing it
FR2533370A1 (fr) * 1982-09-22 1984-03-23 American Micro Syst Procede de fabrication d'un dispositif mos a contacts auto-alignes
GB2128807A (en) * 1982-09-22 1984-05-02 American Micro Syst Improvements in or relating to a method for fabricating an MOS device
EP0200372A3 (en) * 1985-04-02 1988-04-27 Inmos Corporation Self-aligned contact window formation in an integrated circuit
EP0521634A3 (en) * 1991-07-02 1993-05-12 Hewlett-Packard Company Improved thermal inkjet printhead structure and method for making the same
GB2381657A (en) * 2001-06-19 2003-05-07 Samsung Electronics Co Ltd Borderless contact structure
GB2381657B (en) * 2001-06-19 2004-03-03 Samsung Electronics Co Ltd Semiconductor device with borderless contact structure and method of manufacturing the same

Also Published As

Publication number Publication date
FR2446011A1 (fr) 1980-08-01
CA1131796A (en) 1982-09-14
DE3000121A1 (de) 1980-07-17
NL7908534A (nl) 1980-07-10
IT8019078A0 (it) 1980-01-08
FR2446011B3 (enExample) 1981-11-06
JPS5593271A (en) 1980-07-15

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Legal Events

Date Code Title Description
WAP Application withdrawn, taken to be withdrawn or refused ** after publication under section 16(1)