ES8600668A1 - Procedimiento para producir dispositivos semiconductores de oxido metalico de silicio para gigabitios - Google Patents
Procedimiento para producir dispositivos semiconductores de oxido metalico de silicio para gigabitiosInfo
- Publication number
- ES8600668A1 ES8600668A1 ES538085A ES538085A ES8600668A1 ES 8600668 A1 ES8600668 A1 ES 8600668A1 ES 538085 A ES538085 A ES 538085A ES 538085 A ES538085 A ES 538085A ES 8600668 A1 ES8600668 A1 ES 8600668A1
- Authority
- ES
- Spain
- Prior art keywords
- substrate
- oxide
- semiconductor device
- metal
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title 1
- 229910052710 silicon Inorganic materials 0.000 title 1
- 239000010703 silicon Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 abstract 4
- 239000011810 insulating material Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 230000001590 oxidative effect Effects 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 abstract 1
- 125000006850 spacer group Chemical group 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
- H01L29/41783—Raised source or drain electrodes self aligned with the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/981—Utilizing varying dielectric thickness
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
PROCEDIMIENTOS PQARA PRODUCIR DISPOSITIVOS SEMICONDUCTORES DE OXIDO METALICO DE SILICIO.COMPRENDE LAS ETAPAS DE: A) FORMAR UNA REGION DE CANAL EN UN SUBSTRATO SEMICONDUCTOR DE UN PRIMER TIPO DE CONDUCTIVIDAD, TENIENDO DICHO SUBSTRATO UNA MESETA DE MATERIAL SEMICONDUCTOR SOBRE SI; B) FABRICAR, PARA LA REDUCCION DE LA CAPACIDAD PARASTITA, UN ESPACIADOR DE MATERIAL AISLANTE EN CONTACTO CON LOS LADOS DE LA MESETA Y PORCIONES DE LAS SUPERFICIES EXPUESTAS DEL SUBSTRATO; C) IMPLANTAR PRIMEROS IONES DOPANTES POR LO MENOS EN LA SUPERFICIE EXPUESTA DEL SUBSTRATO; Y D) CALENTAR LA MESETA Y EL SUBSTRATO PARA DIFUNDIR LOS IONES DOPANTES EN EL SUBSTRATO, DEFINIENDO DE ESTE MODO LA REGION DELCANAL EN EL SUBSTRATO ENTRE REGIONES DE UN SEGUNDO TIPO DE CONDUCTIVIDAD, SIENDO LA REGION DEL CANAL VIRTUALMENTE COEXTENSIVA DE LA MESETA.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/557,638 US4532697A (en) | 1983-12-02 | 1983-12-02 | Silicon gigabit metal-oxide-semiconductor device processing |
Publications (2)
Publication Number | Publication Date |
---|---|
ES538085A0 ES538085A0 (es) | 1985-11-01 |
ES8600668A1 true ES8600668A1 (es) | 1985-11-01 |
Family
ID=24226286
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES538085A Expired ES8600668A1 (es) | 1983-12-02 | 1984-11-29 | Procedimiento para producir dispositivos semiconductores de oxido metalico de silicio para gigabitios |
Country Status (8)
Country | Link |
---|---|
US (1) | US4532697A (es) |
EP (2) | EP0150582B1 (es) |
JP (1) | JPS61500576A (es) |
KR (1) | KR910006162B1 (es) |
CA (1) | CA1216374A (es) |
DE (1) | DE3479365D1 (es) |
ES (1) | ES8600668A1 (es) |
WO (1) | WO1985002494A1 (es) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5610089A (en) * | 1983-12-26 | 1997-03-11 | Hitachi, Ltd. | Method of fabrication of semiconductor integrated circuit device |
US5276346A (en) * | 1983-12-26 | 1994-01-04 | Hitachi, Ltd. | Semiconductor integrated circuit device having protective/output elements and internal circuits |
US4603472A (en) * | 1984-04-19 | 1986-08-05 | Siemens Aktiengesellschaft | Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation |
US5352620A (en) * | 1984-05-23 | 1994-10-04 | Hitachi, Ltd. | Method of making semiconductor device with memory cells and peripheral transistors |
US4918501A (en) * | 1984-05-23 | 1990-04-17 | Hitachi, Ltd. | Semiconductor device and method of producing the same |
US4947225A (en) * | 1986-04-28 | 1990-08-07 | Rockwell International Corporation | Sub-micron devices with method for forming sub-micron contacts |
US5043778A (en) * | 1986-08-11 | 1991-08-27 | Texas Instruments Incorporated | Oxide-isolated source/drain transistor |
EP0332101B1 (en) * | 1988-03-11 | 1997-06-04 | Fujitsu Limited | Semiconductor device having a region doped to a level exceeding the solubility limit |
US5270224A (en) * | 1988-03-11 | 1993-12-14 | Fujitsu Limited | Method of manufacturing a semiconductor device having a region doped to a level exceeding the solubility limit |
US5518937A (en) * | 1988-03-11 | 1996-05-21 | Fujitsu Limited | Semiconductor device having a region doped to a level exceeding the solubility limit |
US4998150A (en) * | 1988-12-22 | 1991-03-05 | Texas Instruments Incorporated | Raised source/drain transistor |
US5874341A (en) * | 1996-10-30 | 1999-02-23 | Advanced Micro Devices, Inc. | Method of forming trench transistor with source contact in trench |
US5330925A (en) * | 1992-06-18 | 1994-07-19 | At&T Bell Laboratories | Method for making a MOS device |
US5801075A (en) * | 1996-10-30 | 1998-09-01 | Advanced Micro Devices, Inc. | Method of forming trench transistor with metal spacers |
US6054356A (en) * | 1996-12-10 | 2000-04-25 | Advanced Micro Devices, Inc. | Transistor and process of making a transistor having an improved LDD masking material |
US5994737A (en) | 1997-10-16 | 1999-11-30 | Citizen Watch Co, Ltd. | Semiconductor device with bird's beak |
TWI260717B (en) * | 2004-05-17 | 2006-08-21 | Mosel Vitelic Inc | Ion-implantation method for forming a shallow junction |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE1927645B2 (de) * | 1968-06-05 | 1972-10-26 | Matsushita Electronics Corp., Osaka (Japan) | Verfahren zum Herstellen eines MOS-Feldeffekttransistors |
JPS6041470B2 (ja) * | 1976-06-15 | 1985-09-17 | 松下電器産業株式会社 | 半導体装置の製造方法 |
JPS55138877A (en) * | 1979-04-17 | 1980-10-30 | Seiko Instr & Electronics Ltd | Method of fabricating semiconductor device |
DE2926874A1 (de) * | 1979-07-03 | 1981-01-22 | Siemens Ag | Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie |
US4356623A (en) * | 1980-09-15 | 1982-11-02 | Texas Instruments Incorporated | Fabrication of submicron semiconductor devices |
DE3175081D1 (en) * | 1980-12-12 | 1986-09-11 | Toshiba Kk | Method of manufacturing a semiconductor device of the mis type |
US4419810A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Self-aligned field effect transistor process |
US4417385A (en) * | 1982-08-09 | 1983-11-29 | General Electric Company | Processes for manufacturing insulated-gate semiconductor devices with integral shorts |
-
1983
- 1983-12-02 US US06/557,638 patent/US4532697A/en not_active Expired - Lifetime
-
1984
- 1984-11-21 CA CA000468323A patent/CA1216374A/en not_active Expired
- 1984-11-27 EP EP84308209A patent/EP0150582B1/en not_active Expired
- 1984-11-28 WO PCT/US1984/001958 patent/WO1985002494A1/en active IP Right Grant
- 1984-11-28 DE DE8585900350T patent/DE3479365D1/de not_active Expired
- 1984-11-28 EP EP85900350A patent/EP0163729B1/en not_active Expired
- 1984-11-28 KR KR1019850700142A patent/KR910006162B1/ko not_active IP Right Cessation
- 1984-11-28 JP JP59504441A patent/JPS61500576A/ja active Pending
- 1984-11-29 ES ES538085A patent/ES8600668A1/es not_active Expired
Also Published As
Publication number | Publication date |
---|---|
ES538085A0 (es) | 1985-11-01 |
KR910006162B1 (ko) | 1991-08-16 |
WO1985002494A1 (en) | 1985-06-06 |
EP0163729A1 (en) | 1985-12-11 |
EP0150582A1 (en) | 1985-08-07 |
CA1216374A (en) | 1987-01-06 |
EP0150582B1 (en) | 1989-08-23 |
US4532697A (en) | 1985-08-06 |
KR850700182A (ko) | 1985-10-25 |
EP0163729B1 (en) | 1989-08-09 |
JPS61500576A (ja) | 1986-03-27 |
DE3479365D1 (en) | 1989-09-14 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
FD1A | Patent lapsed |
Effective date: 19990405 |