ES538085A0 - Procedimiento para producir dispositivos semiconductores de oxido metalico de silicio para gigabitios - Google Patents

Procedimiento para producir dispositivos semiconductores de oxido metalico de silicio para gigabitios

Info

Publication number
ES538085A0
ES538085A0 ES538085A ES538085A ES538085A0 ES 538085 A0 ES538085 A0 ES 538085A0 ES 538085 A ES538085 A ES 538085A ES 538085 A ES538085 A ES 538085A ES 538085 A0 ES538085 A0 ES 538085A0
Authority
ES
Spain
Prior art keywords
gigabites
procedure
metallic oxide
producing silicon
semiconducting devices
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
ES538085A
Other languages
English (en)
Other versions
ES8600668A1 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of ES8600668A1 publication Critical patent/ES8600668A1/es
Publication of ES538085A0 publication Critical patent/ES538085A0/es
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843Source or drain regions of field-effect devices
    • H01L29/0847Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321After treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725Source or drain electrodes for field effect devices
    • H01L29/41775Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783Raised source or drain electrodes self aligned with the gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/981Utilizing varying dielectric thickness

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
ES538085A 1983-12-02 1984-11-29 Procedimiento para producir dispositivos semiconductores de oxido metalico de silicio para gigabitios Granted ES538085A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/557,638 US4532697A (en) 1983-12-02 1983-12-02 Silicon gigabit metal-oxide-semiconductor device processing

Publications (2)

Publication Number Publication Date
ES8600668A1 ES8600668A1 (es) 1985-11-01
ES538085A0 true ES538085A0 (es) 1985-11-01

Family

ID=24226286

Family Applications (1)

Application Number Title Priority Date Filing Date
ES538085A Granted ES538085A0 (es) 1983-12-02 1984-11-29 Procedimiento para producir dispositivos semiconductores de oxido metalico de silicio para gigabitios

Country Status (8)

Country Link
US (1) US4532697A (es)
EP (2) EP0150582B1 (es)
JP (1) JPS61500576A (es)
KR (1) KR910006162B1 (es)
CA (1) CA1216374A (es)
DE (1) DE3479365D1 (es)
ES (1) ES538085A0 (es)
WO (1) WO1985002494A1 (es)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5610089A (en) * 1983-12-26 1997-03-11 Hitachi, Ltd. Method of fabrication of semiconductor integrated circuit device
US5276346A (en) * 1983-12-26 1994-01-04 Hitachi, Ltd. Semiconductor integrated circuit device having protective/output elements and internal circuits
US4603472A (en) * 1984-04-19 1986-08-05 Siemens Aktiengesellschaft Method of making MOS FETs using silicate glass layer as gate edge masking for ion implantation
US4918501A (en) * 1984-05-23 1990-04-17 Hitachi, Ltd. Semiconductor device and method of producing the same
US5352620A (en) * 1984-05-23 1994-10-04 Hitachi, Ltd. Method of making semiconductor device with memory cells and peripheral transistors
US4947225A (en) * 1986-04-28 1990-08-07 Rockwell International Corporation Sub-micron devices with method for forming sub-micron contacts
US5043778A (en) * 1986-08-11 1991-08-27 Texas Instruments Incorporated Oxide-isolated source/drain transistor
US5270224A (en) * 1988-03-11 1993-12-14 Fujitsu Limited Method of manufacturing a semiconductor device having a region doped to a level exceeding the solubility limit
EP0332101B1 (en) * 1988-03-11 1997-06-04 Fujitsu Limited Semiconductor device having a region doped to a level exceeding the solubility limit
US5518937A (en) * 1988-03-11 1996-05-21 Fujitsu Limited Semiconductor device having a region doped to a level exceeding the solubility limit
US4998150A (en) * 1988-12-22 1991-03-05 Texas Instruments Incorporated Raised source/drain transistor
US5874341A (en) * 1996-10-30 1999-02-23 Advanced Micro Devices, Inc. Method of forming trench transistor with source contact in trench
US5330925A (en) * 1992-06-18 1994-07-19 At&T Bell Laboratories Method for making a MOS device
US5801075A (en) * 1996-10-30 1998-09-01 Advanced Micro Devices, Inc. Method of forming trench transistor with metal spacers
US6054356A (en) * 1996-12-10 2000-04-25 Advanced Micro Devices, Inc. Transistor and process of making a transistor having an improved LDD masking material
US5994737A (en) 1997-10-16 1999-11-30 Citizen Watch Co, Ltd. Semiconductor device with bird's beak
TWI260717B (en) * 2004-05-17 2006-08-21 Mosel Vitelic Inc Ion-implantation method for forming a shallow junction

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE1927645B2 (de) * 1968-06-05 1972-10-26 Matsushita Electronics Corp., Osaka (Japan) Verfahren zum Herstellen eines MOS-Feldeffekttransistors
JPS6041470B2 (ja) * 1976-06-15 1985-09-17 松下電器産業株式会社 半導体装置の製造方法
JPS55138877A (en) * 1979-04-17 1980-10-30 Seiko Instr & Electronics Ltd Method of fabricating semiconductor device
DE2926874A1 (de) * 1979-07-03 1981-01-22 Siemens Ag Verfahren zum herstellen von niederohmigen, diffundierten bereichen bei der silizium-gate-technologie
US4356623A (en) * 1980-09-15 1982-11-02 Texas Instruments Incorporated Fabrication of submicron semiconductor devices
DE3175081D1 (en) * 1980-12-12 1986-09-11 Toshiba Kk Method of manufacturing a semiconductor device of the mis type
US4419810A (en) * 1981-12-30 1983-12-13 International Business Machines Corporation Self-aligned field effect transistor process
US4417385A (en) * 1982-08-09 1983-11-29 General Electric Company Processes for manufacturing insulated-gate semiconductor devices with integral shorts

Also Published As

Publication number Publication date
EP0150582B1 (en) 1989-08-23
WO1985002494A1 (en) 1985-06-06
JPS61500576A (ja) 1986-03-27
ES8600668A1 (es) 1985-11-01
DE3479365D1 (en) 1989-09-14
CA1216374A (en) 1987-01-06
EP0150582A1 (en) 1985-08-07
KR850700182A (ko) 1985-10-25
US4532697A (en) 1985-08-06
KR910006162B1 (ko) 1991-08-16
EP0163729B1 (en) 1989-08-09
EP0163729A1 (en) 1985-12-11

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19990405