ES8800481A1 - Memoria dinamica de circuito integrado - Google Patents

Memoria dinamica de circuito integrado

Info

Publication number
ES8800481A1
ES8800481A1 ES555367A ES555367A ES8800481A1 ES 8800481 A1 ES8800481 A1 ES 8800481A1 ES 555367 A ES555367 A ES 555367A ES 555367 A ES555367 A ES 555367A ES 8800481 A1 ES8800481 A1 ES 8800481A1
Authority
ES
Spain
Prior art keywords
conductor
row
memory
low voltage
dynamic memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES555367A
Other languages
English (en)
Spanish (es)
Other versions
ES555367A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
American Telephone and Telegraph Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Telephone and Telegraph Co Inc filed Critical American Telephone and Telegraph Co Inc
Publication of ES8800481A1 publication Critical patent/ES8800481A1/es
Publication of ES555367A0 publication Critical patent/ES555367A0/es
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/24—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
ES555367A 1985-05-28 1986-05-27 Memoria dinamica de circuito integrado Expired ES8800481A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/738,664 US4679172A (en) 1985-05-28 1985-05-28 Dynamic memory with increased data retention time

Publications (2)

Publication Number Publication Date
ES8800481A1 true ES8800481A1 (es) 1987-11-16
ES555367A0 ES555367A0 (es) 1987-11-16

Family

ID=24968956

Family Applications (1)

Application Number Title Priority Date Filing Date
ES555367A Expired ES8800481A1 (es) 1985-05-28 1986-05-27 Memoria dinamica de circuito integrado

Country Status (8)

Country Link
US (1) US4679172A (online.php)
EP (1) EP0223784B1 (online.php)
JP (1) JPS62502922A (online.php)
KR (1) KR940008142B1 (online.php)
CA (1) CA1252564A (online.php)
DE (1) DE3677150D1 (online.php)
ES (1) ES8800481A1 (online.php)
WO (1) WO1986007183A1 (online.php)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07105137B2 (ja) * 1987-11-17 1995-11-13 日本電気株式会社 半導体メモリ
US5007022A (en) * 1987-12-21 1991-04-09 Texas Instruments Incorporated Two-port two-transistor DRAM
US4914631A (en) * 1988-09-30 1990-04-03 Micron Technology, Inc. Pull up circuit for sense lines in a semiconductor memory
US4924442A (en) * 1988-09-30 1990-05-08 Micron Technology, Inc. Pull up circuit for digit lines in a semiconductor memory
JPH07105140B2 (ja) * 1988-12-16 1995-11-13 日本電気株式会社 半導体メモリ
US5063304A (en) * 1990-04-27 1991-11-05 Texas Instruments Incorporated Integrated circuit with improved on-chip power supply control
US5395784A (en) * 1993-04-14 1995-03-07 Industrial Technology Research Institute Method of manufacturing low leakage and long retention time DRAM
JP3569310B2 (ja) * 1993-10-14 2004-09-22 株式会社ルネサステクノロジ 半導体記憶装置
CH688210A5 (de) * 1993-12-15 1997-06-13 Balzers Hochvakuum Druckmessverfahren und Druckmessanordnung zu dessen Ausfuehrung
US5412606A (en) * 1994-03-29 1995-05-02 At&T Corp. Memory precharge technique
JP3494488B2 (ja) * 1994-11-25 2004-02-09 株式会社ルネサステクノロジ 半導体装置
US5731960A (en) * 1996-09-19 1998-03-24 Bay Networks, Inc. Low inductance decoupling capacitor arrangement
US5949720A (en) * 1998-10-30 1999-09-07 Stmicroelectronics, Inc. Voltage clamping method and apparatus for dynamic random access memory devices
US6075737A (en) * 1998-12-02 2000-06-13 Micron Technology, Inc. Row decoded biasing of sense amplifier for improved one's margin
KR100429572B1 (ko) * 2001-09-24 2004-05-03 주식회사 하이닉스반도체 반도체 기억장치 및 센스앰프의 구동방법
US6888769B2 (en) * 2002-08-29 2005-05-03 Micron Technology, Inc. Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage
US6934181B2 (en) * 2003-02-06 2005-08-23 International Business Machines Corporation Reducing sub-threshold leakage in a memory array

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2454988C2 (de) * 1974-11-20 1976-09-09 Siemens Ag Schaltungsanordnung zur verhinderung des verlustes der in den kapazitaeten von nach dem dynamischen prinzip aufgebauten speicherzellen eines mos- speichers gespeicherten informationen
JPS5313899A (en) * 1976-07-24 1978-02-07 Utsuno Seijiyu Rotary display rack
JPS5399736A (en) * 1977-02-10 1978-08-31 Toshiba Corp Semiconductor memory unit
JPS56114196A (en) * 1980-02-13 1981-09-08 Sharp Corp Ram circuit
JPS601712B2 (ja) * 1980-12-04 1985-01-17 株式会社東芝 半導体記憶装置
JPS58189898A (ja) * 1982-04-30 1983-11-05 Toshiba Corp ダイナミツク記憶装置
US4551641A (en) * 1983-11-23 1985-11-05 Motorola, Inc. Sense amplifier
JPS60191499A (ja) * 1984-03-09 1985-09-28 Toshiba Corp ダイナミツク型ランダムアクセスメモリ

Also Published As

Publication number Publication date
US4679172A (en) 1987-07-07
EP0223784A1 (en) 1987-06-03
CA1252564A (en) 1989-04-11
KR940008142B1 (ko) 1994-09-03
ES555367A0 (es) 1987-11-16
JPH0470718B2 (online.php) 1992-11-11
DE3677150D1 (de) 1991-02-28
WO1986007183A1 (en) 1986-12-04
EP0223784B1 (en) 1991-01-23
KR880700429A (ko) 1988-03-15
JPS62502922A (ja) 1987-11-19

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19971001