ES8601518A1 - Una instalacion de tratamiento de datos - Google Patents

Una instalacion de tratamiento de datos

Info

Publication number
ES8601518A1
ES8601518A1 ES536183A ES536183A ES8601518A1 ES 8601518 A1 ES8601518 A1 ES 8601518A1 ES 536183 A ES536183 A ES 536183A ES 536183 A ES536183 A ES 536183A ES 8601518 A1 ES8601518 A1 ES 8601518A1
Authority
ES
Spain
Prior art keywords
processor
busy
data processing
processing system
system including
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES536183A
Other languages
English (en)
Other versions
ES536183A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of ES8601518A1 publication Critical patent/ES8601518A1/es
Publication of ES536183A0 publication Critical patent/ES536183A0/es
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
    • G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0793—Remedial or corrective actions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • Hardware Redundancy (AREA)
  • Bus Control (AREA)
  • Debugging And Monitoring (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)
  • Selective Calling Equipment (AREA)
  • Inspection Of Paper Currency And Valuable Securities (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Multi-Process Working Machines And Systems (AREA)

Abstract

UNA INSTALACION DE TRATAMIENTO DE DATOS. INCLUYE UN PROCESADOR PRINCIPAL Y UN COPROCESADOR UN CIRCUITO LOGICO ESTA ACOPLADO PARA RECIBIR SALIDAS DE ERROR Y DE ESTADO OCUPADO DEL COPROCESADOR PARA GENERAR UNA SALIDA DE INTERRUPCION CON LA COINCIDENCIA DE LAS SEÑALES ACTIVAS DE ERROR Y ESTANDO OCUPADO Y PARA ENCLAVAR LA SEÑAL DE OCUPACION AL PROCESADOR PRINCIPAL PARA ASEGURAR EL PROCESADOR PRINCIPAL ACEPTARA LA INTERRUPCION ANTES DE EJECUTAR OTRA INSTRUCCION DEL COPROCESADOR.
ES536183A 1983-12-30 1984-09-24 Una instalacion de tratamiento de datos Granted ES536183A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/567,296 US4598356A (en) 1983-12-30 1983-12-30 Data processing system including a main processor and a co-processor and co-processor error handling logic

Publications (2)

Publication Number Publication Date
ES8601518A1 true ES8601518A1 (es) 1985-10-16
ES536183A0 ES536183A0 (es) 1985-10-16

Family

ID=24266577

Family Applications (1)

Application Number Title Priority Date Filing Date
ES536183A Granted ES536183A0 (es) 1983-12-30 1984-09-24 Una instalacion de tratamiento de datos

Country Status (15)

Country Link
US (1) US4598356A (es)
EP (1) EP0147599B1 (es)
JP (1) JPS60146358A (es)
KR (1) KR890003985B1 (es)
AT (1) ATE50371T1 (es)
AU (1) AU567767B2 (es)
BR (1) BR8406635A (es)
CA (1) CA1216949A (es)
DE (1) DE3481351D1 (es)
ES (1) ES536183A0 (es)
GB (1) GB8431010D0 (es)
HK (1) HK81590A (es)
MX (1) MX157706A (es)
PH (1) PH24536A (es)
SG (1) SG67090G (es)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4814977A (en) * 1983-10-18 1989-03-21 S&C Electric Company Apparatus and method for direct memory to peripheral and peripheral to memory data transfers
US4870614A (en) * 1984-08-02 1989-09-26 Quatse Jesse T Programmable controller ("PC") with co-processing architecture
JPS62214464A (ja) * 1986-03-17 1987-09-21 Hitachi Ltd データ処理システム
AU597980B2 (en) * 1986-05-30 1990-06-14 Honeywell Bull Inc. Apparatus and method for interprocessor communication
US5193159A (en) * 1986-09-24 1993-03-09 Hitachi, Ltd. Microprocessor system
JPS6381554A (ja) * 1986-09-25 1988-04-12 Canon Inc 交換可能な周辺装置を取り扱う電子機器
US5109329A (en) * 1987-02-06 1992-04-28 At&T Bell Laboratories Multiprocessing method and arrangement
US4811200A (en) * 1987-05-12 1989-03-07 Motorola, Inc. Multiple microprocessor watchdog system
US5226122A (en) * 1987-08-21 1993-07-06 Compaq Computer Corp. Programmable logic system for filtering commands to a microprocessor
JPH0679307B2 (ja) * 1987-10-22 1994-10-05 日本電気株式会社 コプロセッサの並行動作制御方式
US4908502A (en) * 1988-02-08 1990-03-13 Pitney Bowes Inc. Fault tolerant smart card
EP0335990B1 (en) * 1988-04-02 1993-12-08 International Business Machines Corporation Processor-processor synchronization
US5109514A (en) * 1988-07-28 1992-04-28 Sun Microsystems, Inc. Method and apparatus for executing concurrent CO processor operations and precisely handling related exceptions
GB2225882A (en) * 1988-12-06 1990-06-13 Flare Technology Limited Computer bus structure for multiple processors
US5134693A (en) * 1989-01-18 1992-07-28 Intel Corporation System for handling occurrence of exceptions during execution of microinstructions while running floating point and non-floating point instructions in parallel
US5590363A (en) * 1989-04-18 1996-12-31 Dell Usa, L.P. Circuit for detection of co-processor unit presence and for correction of its absence
US5134713A (en) * 1989-05-19 1992-07-28 Compaq Computer Corporation Coprocessor detection circuit
US5125093A (en) * 1990-08-14 1992-06-23 Nexgen Microsystems Interrupt control for multiprocessor computer system
JPH09293056A (ja) * 1996-04-25 1997-11-11 Aiwa Co Ltd データ処理装置
DE19749068B4 (de) * 1997-11-06 2005-03-10 Bosch Gmbh Robert Verfahren und Vorrichtung zur Überwachung eines Rechnersystems bestehend aus wenigstens zwei Prozessoren
US6009389A (en) * 1997-11-14 1999-12-28 Cirrus Logic, Inc. Dual processor audio decoder and methods with sustained data pipelining during error conditions
US6408407B1 (en) * 1999-06-03 2002-06-18 Ncr Corporation Methods and apparatus for delegated error handling
US8250412B2 (en) * 2003-09-26 2012-08-21 Ati Technologies Ulc Method and apparatus for monitoring and resetting a co-processor
US7702955B2 (en) 2005-12-28 2010-04-20 De Almeida Adrian S Method and apparatus for detecting a fault condition and restoration thereafter using user context information

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3864670A (en) * 1970-09-30 1975-02-04 Yokogawa Electric Works Ltd Dual computer system with signal exchange system
US3786430A (en) * 1971-11-15 1974-01-15 Ibm Data processing system including a small auxiliary processor for overcoming the effects of faulty hardware
US3771131A (en) * 1972-04-17 1973-11-06 Xerox Corp Operating condition monitoring in digital computers
US3866184A (en) * 1973-08-31 1975-02-11 Gte Automatic Electric Lab Inc Timing monitor circuit for central data processor of digital communication system
US3882455A (en) * 1973-09-14 1975-05-06 Gte Automatic Electric Lab Inc Configuration control circuit for control and maintenance complex of digital communications system
JPS5426330B2 (es) * 1974-02-08 1979-09-03
JPS5426330U (es) * 1977-07-25 1979-02-21
US4253183A (en) * 1979-05-02 1981-02-24 Ncr Corporation Method and apparatus for diagnosing faults in a processor having a pipeline architecture
US4392201A (en) * 1980-12-31 1983-07-05 Honeywell Information Systems Inc. Diagnostic subsystem for a cache memory
JPS57212549A (en) * 1981-06-25 1982-12-27 Fujitsu Ltd Information processing device
AU9144782A (en) * 1981-12-21 1983-06-30 General Electric Company Primary and secondary computer system
JPS58168170A (ja) * 1982-03-29 1983-10-04 Fujitsu Ltd 多重プロセツサ
JPS58205395A (ja) * 1982-05-25 1983-11-30 Sony Corp リモ−トコントロ−ル装置

Also Published As

Publication number Publication date
ATE50371T1 (de) 1990-02-15
EP0147599A3 (en) 1987-05-27
SG67090G (en) 1990-09-21
EP0147599B1 (en) 1990-02-07
GB8431010D0 (en) 1985-01-16
AU567767B2 (en) 1987-12-03
HK81590A (en) 1990-10-19
US4598356A (en) 1986-07-01
KR850005116A (ko) 1985-08-21
MX157706A (es) 1988-12-09
KR890003985B1 (ko) 1989-10-14
PH24536A (en) 1990-08-03
AU3409984A (en) 1985-07-04
ES536183A0 (es) 1985-10-16
JPH02732B2 (es) 1990-01-09
DE3481351D1 (de) 1990-03-15
EP0147599A2 (en) 1985-07-10
CA1216949A (en) 1987-01-20
JPS60146358A (ja) 1985-08-02
BR8406635A (pt) 1985-10-15

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 20050620